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1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller8 9maintainers:10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>11 12description:13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware14 to route interrupts across various subsystems. It involves a three-level15 addressing scheme called protocol, client and signal. For example, consider an16 entity on the Application Processor Subsystem (APSS) that wants to listen to17 Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such18 a case, the client would be Modem (client-id is 2) and the signal would be19 SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)20 protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h21 for the list of such IDs.22 23properties:24 compatible:25 items:26 - enum:27 - qcom,qcs8300-ipcc28 - qcom,qdu1000-ipcc29 - qcom,sa8255p-ipcc30 - qcom,sa8775p-ipcc31 - qcom,sc7280-ipcc32 - qcom,sc8280xp-ipcc33 - qcom,sdx75-ipcc34 - qcom,sm6350-ipcc35 - qcom,sm6375-ipcc36 - qcom,sm8250-ipcc37 - qcom,sm8350-ipcc38 - qcom,sm8450-ipcc39 - qcom,sm8550-ipcc40 - qcom,sm8650-ipcc41 - qcom,x1e80100-ipcc42 - const: qcom,ipcc43 44 reg:45 maxItems: 146 47 interrupts:48 maxItems: 149 50 interrupt-controller: true51 52 "#interrupt-cells":53 const: 354 description:55 The first cell is the client-id, the second cell is the signal-id and the56 third cell is the interrupt type.57 58 "#mbox-cells":59 const: 260 description:61 The first cell is the client-id, and the second cell is the signal-id.62 63required:64 - compatible65 - reg66 - interrupts67 - interrupt-controller68 - "#interrupt-cells"69 - "#mbox-cells"70 71additionalProperties: false72 73examples:74 - |75 #include <dt-bindings/interrupt-controller/arm-gic.h>76 #include <dt-bindings/mailbox/qcom-ipcc.h>77 78 mailbox@408000 {79 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";80 reg = <0x408000 0x1000>;81 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;82 interrupt-controller;83 #interrupt-cells = <3>;84 #mbox-cells = <2>;85 };86