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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/allegro,al5e.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allegro DVT Video IP Codecs8 9maintainers:10 - Michael Tretter <m.tretter@pengutronix.de>11 12description: |-13 Allegro DVT video IP codecs present in the Xilinx ZynqMP SoC. The IP core may14 either be a H.264/H.265 encoder or H.264/H.265 decoder ip core.15 16 Each actual codec engine is controlled by a microcontroller (MCU). Host17 software uses a provided mailbox interface to communicate with the MCU. The18 MCUs share an interrupt.19 20properties:21 compatible:22 oneOf:23 - items:24 - const: allegro,al5e-1.125 - const: allegro,al5e26 - items:27 - const: allegro,al5d-1.128 - const: allegro,al5d29 30 reg:31 items:32 - description: The registers33 - description: The SRAM34 35 reg-names:36 items:37 - const: regs38 - const: sram39 40 interrupts:41 maxItems: 142 43 clocks:44 items:45 - description: Core clock46 - description: MCU clock47 - description: Core AXI master port clock48 - description: MCU AXI master port clock49 - description: AXI4-Lite slave port clock50 51 clock-names:52 items:53 - const: core_clk54 - const: mcu_clk55 - const: m_axi_core_aclk56 - const: m_axi_mcu_aclk57 - const: s_axi_lite_aclk58 59required:60 - compatible61 - reg62 - reg-names63 - interrupts64 - clocks65 - clock-names66 67additionalProperties: False68 69examples:70 - |71 fpga {72 #address-cells = <2>;73 #size-cells = <2>;74 75 al5e: video-codec@a0009000 {76 compatible = "allegro,al5e-1.1", "allegro,al5e";77 reg = <0 0xa0009000 0 0x1000>,78 <0 0xa0000000 0 0x8000>;79 reg-names = "regs", "sram";80 interrupts = <0 96 4>;81 clocks = <&xlnx_vcu 0>, <&xlnx_vcu 1>,82 <&clkc 71>, <&clkc 71>, <&clkc 71>;83 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",84 "m_axi_mcu_aclk", "s_axi_lite_aclk";85 };86 };87 - |88 fpga {89 #address-cells = <2>;90 #size-cells = <2>;91 92 al5d: video-codec@a0029000 {93 compatible = "allegro,al5d-1.1", "allegro,al5d";94 reg = <0 0xa0029000 0 0x1000>,95 <0 0xa0020000 0 0x8000>;96 reg-names = "regs", "sram";97 interrupts = <0 96 4>;98 clocks = <&xlnx_vcu 2>, <&xlnx_vcu 3>,99 <&clkc 71>, <&clkc 71>, <&clkc 71>;100 clock-names = "core_clk", "mcu_clk", "m_axi_core_aclk",101 "m_axi_mcu_aclk", "s_axi_lite_aclk";102 };103 };104 105...106