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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A10 CMOS Sensor Interface (CSI)8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13description: |-14 The Allwinner A10 and later has a CMOS Sensor Interface to retrieve15 frames from a parallel or BT656 sensor.16 17properties:18 compatible:19 oneOf:20 - const: allwinner,sun4i-a10-csi121 - const: allwinner,sun7i-a20-csi022 - items:23 - const: allwinner,sun7i-a20-csi124 - const: allwinner,sun4i-a10-csi125 - items:26 - const: allwinner,sun8i-r40-csi027 - const: allwinner,sun7i-a20-csi028 29 reg:30 maxItems: 131 32 interrupts:33 maxItems: 134 35 clocks:36 oneOf:37 - items:38 - description: The CSI interface clock39 - description: The CSI DRAM clock40 41 - items:42 - description: The CSI interface clock43 - description: The CSI ISP clock44 - description: The CSI DRAM clock45 46 clock-names:47 oneOf:48 - items:49 - const: bus50 - const: ram51 52 - items:53 - const: bus54 - const: isp55 - const: ram56 57 resets:58 maxItems: 159 60 # FIXME: This should be made required eventually once every SoC will61 # have the MBUS declared.62 interconnects:63 maxItems: 164 65 # FIXME: This should be made required eventually once every SoC will66 # have the MBUS declared.67 interconnect-names:68 const: dma-mem69 70 port:71 $ref: /schemas/graph.yaml#/$defs/port-base72 additionalProperties: false73 74 properties:75 endpoint:76 $ref: video-interfaces.yaml#77 unevaluatedProperties: false78 79 properties:80 bus-width:81 enum: [8, 16]82 83 data-active: true84 hsync-active: true85 pclk-sample: true86 vsync-active: true87 88 required:89 - bus-width90 - data-active91 - hsync-active92 - pclk-sample93 - vsync-active94 95required:96 - compatible97 - reg98 - interrupts99 - clocks100 101additionalProperties: false102 103examples:104 - |105 #include <dt-bindings/interrupt-controller/arm-gic.h>106 #include <dt-bindings/clock/sun7i-a20-ccu.h>107 #include <dt-bindings/reset/sun4i-a10-ccu.h>108 109 csi0: csi@1c09000 {110 compatible = "allwinner,sun7i-a20-csi0";111 reg = <0x01c09000 0x1000>;112 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;113 clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;114 clock-names = "bus", "isp", "ram";115 resets = <&ccu RST_CSI0>;116 117 port {118 csi_from_ov5640: endpoint {119 remote-endpoint = <&ov5640_to_csi>;120 bus-width = <8>;121 hsync-active = <1>; /* Active high */122 vsync-active = <0>; /* Active low */123 data-active = <1>; /* Active high */124 pclk-sample = <1>; /* Rising */125 };126 };127 };128 129...130