brintos

brintos / linux-shallow public Read only

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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A10 Video Engine8 9maintainers:10  - Chen-Yu Tsai <wens@csie.org>11  - Maxime Ripard <mripard@kernel.org>12 13properties:14  compatible:15    enum:16      - allwinner,sun4i-a10-video-engine17      - allwinner,sun5i-a13-video-engine18      - allwinner,sun7i-a20-video-engine19      - allwinner,sun8i-a33-video-engine20      - allwinner,sun8i-h3-video-engine21      - allwinner,sun8i-v3s-video-engine22      - allwinner,sun8i-r40-video-engine23      - allwinner,sun20i-d1-video-engine24      - allwinner,sun50i-a64-video-engine25      - allwinner,sun50i-h5-video-engine26      - allwinner,sun50i-h6-video-engine27 28  reg:29    maxItems: 130 31  interrupts:32    maxItems: 133 34  clocks:35    items:36      - description: Bus Clock37      - description: Module Clock38      - description: RAM Clock39 40  clock-names:41    items:42      - const: ahb43      - const: mod44      - const: ram45 46  resets:47    maxItems: 148 49  allwinner,sram:50    $ref: /schemas/types.yaml#/definitions/phandle-array51    items:52      - items:53          - description: phandle to SRAM54          - description: register value for device55    description: Phandle to the device SRAM56 57  iommus:58    maxItems: 159 60  memory-region:61    maxItems: 162    description:63      CMA pool to use for buffers allocation instead of the default64      CMA pool.65 66required:67  - compatible68  - reg69  - interrupts70  - clocks71  - clock-names72  - resets73  - allwinner,sram74 75additionalProperties: false76 77examples:78  - |79    #include <dt-bindings/interrupt-controller/arm-gic.h>80    #include <dt-bindings/clock/sun7i-a20-ccu.h>81    #include <dt-bindings/reset/sun4i-a10-ccu.h>82 83    video-codec@1c0e000 {84        compatible = "allwinner,sun7i-a20-video-engine";85        reg = <0x01c0e000 0x1000>;86        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;87        clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,88                 <&ccu CLK_DRAM_VE>;89        clock-names = "ahb", "mod", "ram";90        resets = <&ccu RST_VE>;91        allwinner,sram = <&ve_sram 1>;92    };93 94...95