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1Cadence MIPI-CSI2 TX controller2===============================3 4The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to54 CSI lanes in output, and up to 4 different pixel streams in input.6 7Required properties:8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.110 - reg: base address and size of the memory mapped region11 - clocks: phandles to the clocks driving the controller12 - clock-names: must contain:13 * esc_clk: escape mode clock14 * p_clk: register bank clock15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream16 implemented in hardware, between 0 and 317 18Optional properties19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set20 - phy-names: must contain "dphy"21 22Required subnodes:23 - ports: A ports node with one port child node per device input and output24 port, in accordance with the video interface bindings defined in25 Documentation/devicetree/bindings/media/video-interfaces.txt. The26 port nodes are numbered as follows.27 28 Port Description29 -----------------------------30 0 CSI-2 output31 1 Stream 0 input32 2 Stream 1 input33 3 Stream 2 input34 4 Stream 3 input35 36 The stream input port nodes are optional if they are not37 connected to anything at the hardware level or implemented38 in the design. Since there is only one endpoint per port,39 the endpoints are not numbered.40 41Example:42 43csi2tx: csi-bridge@0d0e1000 {44 compatible = "cdns,csi2tx";45 reg = <0x0d0e1000 0x1000>;46 clocks = <&byteclock>, <&byteclock>,47 <&coreclock>, <&coreclock>,48 <&coreclock>, <&coreclock>;49 clock-names = "p_clk", "esc_clk",50 "pixel_if0_clk", "pixel_if1_clk",51 "pixel_if2_clk", "pixel_if3_clk";52 53 ports {54 #address-cells = <1>;55 #size-cells = <0>;56 57 port@0 {58 reg = <0>;59 60 csi2tx_out: endpoint {61 remote-endpoint = <&remote_in>;62 clock-lanes = <0>;63 data-lanes = <1 2>;64 };65 };66 67 port@1 {68 reg = <1>;69 70 csi2tx_in_stream0: endpoint {71 remote-endpoint = <&stream0_out>;72 };73 };74 75 port@2 {76 reg = <2>;77 78 csi2tx_in_stream1: endpoint {79 remote-endpoint = <&stream1_out>;80 };81 };82 83 port@3 {84 reg = <3>;85 86 csi2tx_in_stream2: endpoint {87 remote-endpoint = <&stream2_out>;88 };89 };90 91 port@4 {92 reg = <4>;93 94 csi2tx_in_stream3: endpoint {95 remote-endpoint = <&stream3_out>;96 };97 };98 };99};100