89 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 3%YAML 1.24---5$id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Freescale Pixel Pipeline9 10maintainers:11 - Philipp Zabel <p.zabel@pengutronix.de>12 - Michael Tretter <m.tretter@pengutronix.de>13 14description:15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine16 that supports scaling, colorspace conversion, alpha blending, rotation, and17 pixel conversion via lookup table. Different versions are present on various18 i.MX SoCs from i.MX23 to i.MX7.19 20properties:21 compatible:22 oneOf:23 - enum:24 - fsl,imx6ul-pxp25 - fsl,imx6ull-pxp26 - fsl,imx7d-pxp27 - items:28 - enum:29 - fsl,imx6sll-pxp30 - fsl,imx6sx-pxp31 - const: fsl,imx6ull-pxp32 33 reg:34 maxItems: 135 36 interrupts:37 minItems: 138 maxItems: 239 40 clocks:41 maxItems: 142 43 clock-names:44 const: axi45 46 power-domains:47 maxItems: 148 49required:50 - compatible51 - reg52 - interrupts53 - clocks54 - clock-names55 56allOf:57 - if:58 properties:59 compatible:60 contains:61 enum:62 - fsl,imx6sx-pxp63 - fsl,imx6ul-pxp64 then:65 properties:66 interrupts:67 maxItems: 168 else:69 properties:70 interrupts:71 minItems: 272 maxItems: 273 74additionalProperties: false75 76examples:77 - |78 #include <dt-bindings/clock/imx6ul-clock.h>79 #include <dt-bindings/interrupt-controller/arm-gic.h>80 81 pxp: pxp@21cc000 {82 compatible = "fsl,imx6ull-pxp";83 reg = <0x021cc000 0x4000>;84 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,85 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;86 clock-names = "axi";87 clocks = <&clks IMX6UL_CLK_PXP>;88 };89