176 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge8 9maintainers:10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>11 - Sylvain Petinot <sylvain.petinot@foss.st.com>12 13description:14 MIPID02 has two CSI-2 input ports, only one of those ports can be15 active at a time. Active port input stream will be de-serialized16 and its content outputted through PARALLEL output port.17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-218 second input port is a single lane 800Mbps. Both ports support clock19 and data lane polarity swap. First port also supports data lane swap.20 PARALLEL output port has a maximum width of 12 bits.21 Supported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888,22 RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.23 24properties:25 compatible:26 const: st,st-mipid0227 28 reg:29 maxItems: 130 31 clocks:32 maxItems: 133 34 clock-names:35 const: xclk36 37 VDDE-supply:38 description:39 Sensor digital IO supply. Must be 1.8 volts.40 41 VDDIN-supply:42 description:43 Sensor internal regulator supply. Must be 1.8 volts.44 45 reset-gpios:46 description:47 Reference to the GPIO connected to the xsdn pin, if any.48 This is an active low signal to the mipid02.49 50 ports:51 $ref: /schemas/graph.yaml#/properties/ports52 properties:53 port@0:54 $ref: /schemas/graph.yaml#/$defs/port-base55 unevaluatedProperties: false56 description: CSI-2 first input port57 properties:58 endpoint:59 $ref: /schemas/media/video-interfaces.yaml#60 unevaluatedProperties: false61 62 properties:63 data-lanes:64 description:65 Single-lane operation shall be <1> or <2> .66 Dual-lane operation shall be <1 2> or <2 1> .67 minItems: 168 maxItems: 269 70 lane-polarities:71 description:72 Any lane can be inverted or not.73 minItems: 174 maxItems: 275 76 required:77 - data-lanes78 79 port@1:80 $ref: /schemas/graph.yaml#/$defs/port-base81 unevaluatedProperties: false82 description: CSI-2 second input port83 properties:84 endpoint:85 $ref: /schemas/media/video-interfaces.yaml#86 unevaluatedProperties: false87 88 properties:89 data-lanes:90 description:91 Single-lane operation shall be <1> or <2> .92 maxItems: 193 94 lane-polarities:95 description:96 Any lane can be inverted or not.97 maxItems: 198 99 required:100 - data-lanes101 102 port@2:103 $ref: /schemas/graph.yaml#/$defs/port-base104 unevaluatedProperties: false105 description: Output port106 properties:107 endpoint:108 $ref: /schemas/media/video-interfaces.yaml#109 unevaluatedProperties: false110 111 properties:112 bus-width:113 enum: [6, 7, 8, 10, 12]114 115 required:116 - bus-width117 118 anyOf:119 - required:120 - port@0121 - required:122 - port@1123 124 required:125 - port@2126 127additionalProperties: false128 129required:130 - compatible131 - reg132 - clocks133 - clock-names134 - VDDE-supply135 - VDDIN-supply136 - ports137 138examples:139 - |140 i2c {141 #address-cells = <1>;142 #size-cells = <0>;143 mipid02: csi2rx@14 {144 compatible = "st,st-mipid02";145 reg = <0x14>;146 clocks = <&clk_ext_camera_12>;147 clock-names = "xclk";148 VDDE-supply = <&vdd>;149 VDDIN-supply = <&vdd>;150 ports {151 #address-cells = <1>;152 #size-cells = <0>;153 port@0 {154 reg = <0>;155 156 ep0: endpoint {157 data-lanes = <1 2>;158 remote-endpoint = <&mipi_csi2_in>;159 };160 };161 port@2 {162 reg = <2>;163 164 ep2: endpoint {165 bus-width = <8>;166 hsync-active = <0>;167 vsync-active = <0>;168 remote-endpoint = <¶llel_out>;169 };170 };171 };172 };173 };174 175...176