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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek Write DMA with Rotation8 9maintainers:10 - Matthias Brugger <matthias.bgg@gmail.com>11 - Moudy Ho <moudy.ho@mediatek.com>12 13description: |14 One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.15 16properties:17 compatible:18 oneOf:19 - enum:20 - mediatek,mt8183-mdp3-wrot21 - items:22 - enum:23 - mediatek,mt8195-mdp3-wrot24 - const: mediatek,mt8183-mdp3-wrot25 26 reg:27 maxItems: 128 29 mediatek,gce-client-reg:30 $ref: /schemas/types.yaml#/definitions/phandle-array31 items:32 items:33 - description: phandle of GCE34 - description: GCE subsys id35 - description: register offset36 - description: register size37 description: The register of client driver can be configured by gce with38 4 arguments defined in this property. Each GCE subsys id is mapping to39 a client defined in the header include/dt-bindings/gce/<chip>-gce.h.40 41 mediatek,gce-events:42 description:43 The event id which is mapping to the specific hardware event signal44 to gce. The event id is defined in the gce header45 include/dt-bindings/gce/<chip>-gce.h of each chips.46 $ref: /schemas/types.yaml#/definitions/uint32-array47 48 power-domains:49 maxItems: 150 51 clocks:52 minItems: 153 54 iommus:55 maxItems: 156 57 '#dma-cells':58 const: 159 60required:61 - compatible62 - reg63 - mediatek,gce-client-reg64 - mediatek,gce-events65 - power-domains66 - clocks67 - iommus68 - '#dma-cells'69 70additionalProperties: false71 72examples:73 - |74 #include <dt-bindings/clock/mt8183-clk.h>75 #include <dt-bindings/gce/mt8183-gce.h>76 #include <dt-bindings/power/mt8183-power.h>77 #include <dt-bindings/memory/mt8183-larb-port.h>78 79 dma-controller@14005000 {80 compatible = "mediatek,mt8183-mdp3-wrot";81 reg = <0x14005000 0x1000>;82 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;83 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,84 <CMDQ_EVENT_MDP_WROT0_EOF>;85 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;86 clocks = <&mmsys CLK_MM_MDP_WROT0>;87 iommus = <&iommu>;88 #dma-cells = <1>;89 };90