141 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegenc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek JPEG Encoder8 9maintainers:10 - kyrie wu <kyrie.wu@mediatek.corp-partner.google.com>11 12description:13 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs14 15properties:16 compatible:17 const: mediatek,mt8195-jpgenc18 19 power-domains:20 maxItems: 121 22 iommus:23 maxItems: 424 description:25 Points to the respective IOMMU block with master port as argument, see26 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.27 Ports are according to the HW.28 29 "#address-cells":30 const: 231 32 "#size-cells":33 const: 234 35 ranges: true36 37# Required child node:38patternProperties:39 "^jpgenc@[0-9a-f]+$":40 type: object41 description:42 The jpeg encoder hardware device node which should be added as subnodes to43 the main jpeg node.44 45 properties:46 compatible:47 const: mediatek,mt8195-jpgenc-hw48 49 reg:50 maxItems: 151 52 iommus:53 minItems: 154 maxItems: 3255 description:56 List of the hardware port in respective IOMMU block for current Socs.57 Refer to bindings/iommu/mediatek,iommu.yaml.58 59 interrupts:60 maxItems: 161 62 clocks:63 maxItems: 164 65 clock-names:66 items:67 - const: jpgenc68 69 power-domains:70 maxItems: 171 72 required:73 - compatible74 - reg75 - iommus76 - interrupts77 - clocks78 - clock-names79 - power-domains80 81 additionalProperties: false82 83required:84 - compatible85 - power-domains86 - iommus87 - ranges88 89additionalProperties: false90 91examples:92 - |93 #include <dt-bindings/interrupt-controller/arm-gic.h>94 #include <dt-bindings/memory/mt8195-memory-port.h>95 #include <dt-bindings/interrupt-controller/irq.h>96 #include <dt-bindings/clock/mt8195-clk.h>97 #include <dt-bindings/power/mt8195-power.h>98 99 soc {100 #address-cells = <2>;101 #size-cells = <2>;102 103 jpgenc-master {104 compatible = "mediatek,mt8195-jpgenc";105 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;106 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,107 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,108 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,109 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;110 #address-cells = <2>;111 #size-cells = <2>;112 ranges;113 114 jpgenc@1a030000 {115 compatible = "mediatek,mt8195-jpgenc-hw";116 reg = <0 0x1a030000 0 0x10000>;117 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,118 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,119 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,120 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;121 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;122 clocks = <&vencsys CLK_VENC_JPGENC>;123 clock-names = "jpgenc";124 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;125 };126 127 jpgenc@1b030000 {128 compatible = "mediatek,mt8195-jpgenc-hw";129 reg = <0 0x1b030000 0 0x10000>;130 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,131 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,132 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,133 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;134 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;135 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;136 clock-names = "jpgenc";137 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;138 };139 };140 };141