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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek JPEG Encoder8 9maintainers:10 - Xia Jiang <xia.jiang@mediatek.com>11 12description: |-13 MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs14 15properties:16 compatible:17 items:18 - enum:19 - mediatek,mt2701-jpgenc20 - mediatek,mt8183-jpgenc21 - mediatek,mt8186-jpgenc22 - mediatek,mt8188-jpgenc23 - const: mediatek,mtk-jpgenc24 reg:25 maxItems: 126 27 interrupts:28 maxItems: 129 30 clocks:31 maxItems: 132 33 clock-names:34 items:35 - const: jpgenc36 37 power-domains:38 maxItems: 139 40 iommus:41 minItems: 242 maxItems: 443 description: |44 Points to the respective IOMMU block with master port as argument, see45 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.46 Ports are according to the HW.47 48required:49 - compatible50 - reg51 - interrupts52 - clocks53 - clock-names54 - power-domains55 - iommus56 57additionalProperties: false58 59examples:60 - |61 #include <dt-bindings/clock/mt2701-clk.h>62 #include <dt-bindings/interrupt-controller/arm-gic.h>63 #include <dt-bindings/memory/mt2701-larb-port.h>64 #include <dt-bindings/power/mt2701-power.h>65 jpegenc: jpegenc@1500a000 {66 compatible = "mediatek,mt2701-jpgenc",67 "mediatek,mtk-jpgenc";68 reg = <0x1500a000 0x1000>;69 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;70 clocks = <&imgsys CLK_IMG_VENC>;71 clock-names = "jpgenc";72 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;73 iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,74 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;75 };76