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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NXP i.MX8MQ MIPI CSI-2 receiver8 9maintainers:10 - Martin Kepplinger <martin.kepplinger@puri.sm>11 12description: |-13 This binding covers the CSI-2 RX PHY and host controller included in the14 NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the15 input imaging devices.16 17properties:18 compatible:19 enum:20 - fsl,imx8mq-mipi-csi221 22 reg:23 maxItems: 124 25 clocks:26 items:27 - description: core is the RX Controller Core Clock input. This clock28 must be exactly equal to or faster than the receive29 byteclock from the RX DPHY.30 - description: esc is the Rx Escape Clock. This must be the same escape31 clock that the RX DPHY receives.32 - description: ui is the pixel clock (phy_ref up to 333Mhz).33 See the reference manual for details.34 35 clock-names:36 items:37 - const: core38 - const: esc39 - const: ui40 41 power-domains:42 maxItems: 143 44 resets:45 items:46 - description: CORE_RESET reset register bit definition47 - description: PHY_REF_RESET reset register bit definition48 - description: ESC_RESET reset register bit definition49 50 fsl,mipi-phy-gpr:51 description: |52 The phandle to the imx8mq syscon iomux-gpr with the register53 for setting RX_ENABLE for the mipi receiver.54 55 The format should be as follows:56 <gpr req_gpr>57 gpr is the phandle to general purpose register node.58 req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.59 $ref: /schemas/types.yaml#/definitions/phandle-array60 items:61 - items:62 - description: The 'gpr' is the phandle to general purpose register node.63 - description: The 'req_gpr' is the gpr register offset containing64 CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.65 maximum: 0xff66 67 interconnects:68 maxItems: 169 70 interconnect-names:71 const: dram72 73 ports:74 $ref: /schemas/graph.yaml#/properties/ports75 76 properties:77 port@0:78 $ref: /schemas/graph.yaml#/$defs/port-base79 unevaluatedProperties: false80 description:81 Input port node, single endpoint describing the CSI-2 transmitter.82 83 properties:84 endpoint:85 $ref: video-interfaces.yaml#86 unevaluatedProperties: false87 88 properties:89 data-lanes:90 minItems: 191 items:92 - const: 193 - const: 294 - const: 395 - const: 496 97 required:98 - data-lanes99 100 port@1:101 $ref: /schemas/graph.yaml#/properties/port102 description:103 Output port node104 105 required:106 - port@0107 - port@1108 109required:110 - compatible111 - reg112 - clocks113 - clock-names114 - power-domains115 - resets116 - fsl,mipi-phy-gpr117 - ports118 119additionalProperties: false120 121examples:122 - |123 #include <dt-bindings/clock/imx8mq-clock.h>124 #include <dt-bindings/interconnect/imx8mq.h>125 #include <dt-bindings/reset/imx8mq-reset.h>126 127 csi@30a70000 {128 compatible = "fsl,imx8mq-mipi-csi2";129 reg = <0x30a70000 0x1000>;130 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,131 <&clk IMX8MQ_CLK_CSI1_ESC>,132 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;133 clock-names = "core", "esc", "ui";134 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,135 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,136 <&clk IMX8MQ_CLK_CSI1_ESC>;137 assigned-clock-rates = <266000000>, <200000000>, <66000000>;138 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,139 <&clk IMX8MQ_SYS2_PLL_1000M>,140 <&clk IMX8MQ_SYS1_PLL_800M>;141 power-domains = <&pgc_mipi_csi1>;142 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,143 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,144 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;145 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;146 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;147 interconnect-names = "dram";148 149 ports {150 #address-cells = <1>;151 #size-cells = <0>;152 153 port@0 {154 reg = <0>;155 156 imx8mm_mipi_csi_in: endpoint {157 remote-endpoint = <&imx477_out>;158 data-lanes = <1 2 3 4>;159 };160 };161 162 port@1 {163 reg = <1>;164 165 imx8mm_mipi_csi_out: endpoint {166 remote-endpoint = <&csi_in>;167 };168 };169 };170 };171 172...173