513 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/qcom,sc8280xp-camss.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm SC8280XP Camera Subsystem (CAMSS)8 9maintainers:10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>11 12description: |13 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.14 15properties:16 compatible:17 const: qcom,sc8280xp-camss18 19 clocks:20 maxItems: 4021 22 clock-names:23 items:24 - const: camnoc_axi25 - const: cpas_ahb26 - const: csiphy027 - const: csiphy0_timer28 - const: csiphy129 - const: csiphy1_timer30 - const: csiphy231 - const: csiphy2_timer32 - const: csiphy333 - const: csiphy3_timer34 - const: vfe0_axi35 - const: vfe036 - const: vfe0_cphy_rx37 - const: vfe0_csid38 - const: vfe1_axi39 - const: vfe140 - const: vfe1_cphy_rx41 - const: vfe1_csid42 - const: vfe2_axi43 - const: vfe244 - const: vfe2_cphy_rx45 - const: vfe2_csid46 - const: vfe3_axi47 - const: vfe348 - const: vfe3_cphy_rx49 - const: vfe3_csid50 - const: vfe_lite051 - const: vfe_lite0_cphy_rx52 - const: vfe_lite0_csid53 - const: vfe_lite154 - const: vfe_lite1_cphy_rx55 - const: vfe_lite1_csid56 - const: vfe_lite257 - const: vfe_lite2_cphy_rx58 - const: vfe_lite2_csid59 - const: vfe_lite360 - const: vfe_lite3_cphy_rx61 - const: vfe_lite3_csid62 - const: gcc_axi_hf63 - const: gcc_axi_sf64 65 interrupts:66 maxItems: 2067 68 interrupt-names:69 items:70 - const: csid1_lite71 - const: vfe_lite172 - const: csiphy373 - const: csid074 - const: vfe075 - const: csid176 - const: vfe177 - const: csid0_lite78 - const: vfe_lite079 - const: csiphy080 - const: csiphy181 - const: csiphy282 - const: csid283 - const: vfe284 - const: csid3_lite85 - const: csid2_lite86 - const: vfe_lite387 - const: vfe_lite288 - const: csid389 - const: vfe390 91 iommus:92 maxItems: 1693 94 interconnects:95 maxItems: 496 97 interconnect-names:98 items:99 - const: cam_ahb100 - const: cam_hf_mnoc101 - const: cam_sf_mnoc102 - const: cam_sf_icp_mnoc103 104 power-domains:105 items:106 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.107 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.108 - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.109 - description: IFE3 GDSC - Image Front End, Global Distributed Switch Controller.110 - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.111 112 power-domain-names:113 items:114 - const: ife0115 - const: ife1116 - const: ife2117 - const: ife3118 - const: top119 120 ports:121 $ref: /schemas/graph.yaml#/properties/ports122 123 description:124 CSI input ports.125 126 properties:127 port@0:128 $ref: /schemas/graph.yaml#/$defs/port-base129 unevaluatedProperties: false130 description:131 Input port for receiving CSI data from CSIPHY0.132 133 properties:134 endpoint:135 $ref: video-interfaces.yaml#136 unevaluatedProperties: false137 138 properties:139 clock-lanes:140 maxItems: 1141 142 data-lanes:143 minItems: 1144 maxItems: 4145 146 required:147 - clock-lanes148 - data-lanes149 150 port@1:151 $ref: /schemas/graph.yaml#/$defs/port-base152 unevaluatedProperties: false153 description:154 Input port for receiving CSI data from CSIPHY1.155 156 properties:157 endpoint:158 $ref: video-interfaces.yaml#159 unevaluatedProperties: false160 161 properties:162 clock-lanes:163 maxItems: 1164 165 data-lanes:166 minItems: 1167 maxItems: 4168 169 required:170 - clock-lanes171 - data-lanes172 173 port@2:174 $ref: /schemas/graph.yaml#/$defs/port-base175 unevaluatedProperties: false176 description:177 Input port for receiving CSI data from CSIPHY2.178 179 properties:180 endpoint:181 $ref: video-interfaces.yaml#182 unevaluatedProperties: false183 184 properties:185 clock-lanes:186 maxItems: 1187 188 data-lanes:189 minItems: 1190 maxItems: 4191 192 required:193 - clock-lanes194 - data-lanes195 196 port@3:197 $ref: /schemas/graph.yaml#/$defs/port-base198 unevaluatedProperties: false199 description:200 Input port for receiving CSI data from CSIPHY3.201 202 properties:203 endpoint:204 $ref: video-interfaces.yaml#205 unevaluatedProperties: false206 207 properties:208 clock-lanes:209 maxItems: 1210 211 data-lanes:212 minItems: 1213 maxItems: 4214 215 required:216 - clock-lanes217 - data-lanes218 219 reg:220 maxItems: 20221 222 reg-names:223 items:224 - const: csiphy2225 - const: csiphy3226 - const: csiphy0227 - const: csiphy1228 - const: vfe0229 - const: csid0230 - const: vfe1231 - const: csid1232 - const: vfe2233 - const: csid2234 - const: vfe_lite0235 - const: csid0_lite236 - const: vfe_lite1237 - const: csid1_lite238 - const: vfe_lite2239 - const: csid2_lite240 - const: vfe_lite3241 - const: csid3_lite242 - const: vfe3243 - const: csid3244 245 vdda-phy-supply:246 description:247 Phandle to a regulator supply to PHY core block.248 249 vdda-pll-supply:250 description:251 Phandle to 1.8V regulator supply to PHY refclk pll block.252 253required:254 - clock-names255 - clocks256 - compatible257 - interconnects258 - interconnect-names259 - interrupts260 - interrupt-names261 - iommus262 - power-domains263 - power-domain-names264 - reg265 - reg-names266 - vdda-phy-supply267 - vdda-pll-supply268 269additionalProperties: false270 271examples:272 - |273 #include <dt-bindings/interrupt-controller/arm-gic.h>274 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>275 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>276 #include <dt-bindings/interconnect/qcom,sc8280xp.h>277 #include <dt-bindings/power/qcom-rpmpd.h>278 279 soc {280 #address-cells = <2>;281 #size-cells = <2>;282 283 camss: camss@ac5a000 {284 compatible = "qcom,sc8280xp-camss";285 286 reg = <0 0x0ac5a000 0 0x2000>,287 <0 0x0ac5c000 0 0x2000>,288 <0 0x0ac65000 0 0x2000>,289 <0 0x0ac67000 0 0x2000>,290 <0 0x0acaf000 0 0x4000>,291 <0 0x0acb3000 0 0x1000>,292 <0 0x0acb6000 0 0x4000>,293 <0 0x0acba000 0 0x1000>,294 <0 0x0acbd000 0 0x4000>,295 <0 0x0acc1000 0 0x1000>,296 <0 0x0acc4000 0 0x4000>,297 <0 0x0acc8000 0 0x1000>,298 <0 0x0accb000 0 0x4000>,299 <0 0x0accf000 0 0x1000>,300 <0 0x0acd2000 0 0x4000>,301 <0 0x0acd6000 0 0x1000>,302 <0 0x0acd9000 0 0x4000>,303 <0 0x0acdd000 0 0x1000>,304 <0 0x0ace0000 0 0x4000>,305 <0 0x0ace4000 0 0x1000>;306 307 reg-names = "csiphy2",308 "csiphy3",309 "csiphy0",310 "csiphy1",311 "vfe0",312 "csid0",313 "vfe1",314 "csid1",315 "vfe2",316 "csid2",317 "vfe_lite0",318 "csid0_lite",319 "vfe_lite1",320 "csid1_lite",321 "vfe_lite2",322 "csid2_lite",323 "vfe_lite3",324 "csid3_lite",325 "vfe3",326 "csid3";327 328 vdda-phy-supply = <&vreg_l6d>;329 vdda-pll-supply = <&vreg_l4d>;330 331 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,332 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,333 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,334 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,335 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,336 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,337 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,338 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,339 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,340 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,341 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,342 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,343 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,344 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,345 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,346 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,347 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,348 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,349 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,350 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;351 352 interrupt-names = "csid1_lite",353 "vfe_lite1",354 "csiphy3",355 "csid0",356 "vfe0",357 "csid1",358 "vfe1",359 "csid0_lite",360 "vfe_lite0",361 "csiphy0",362 "csiphy1",363 "csiphy2",364 "csid2",365 "vfe2",366 "csid3_lite",367 "csid2_lite",368 "vfe_lite3",369 "vfe_lite2",370 "csid3",371 "vfe3";372 373 power-domains = <&camcc IFE_0_GDSC>,374 <&camcc IFE_1_GDSC>,375 <&camcc IFE_2_GDSC>,376 <&camcc IFE_3_GDSC>,377 <&camcc TITAN_TOP_GDSC>;378 379 power-domain-names = "ife0",380 "ife1",381 "ife2",382 "ife3",383 "top";384 385 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,386 <&camcc CAMCC_CPAS_AHB_CLK>,387 <&camcc CAMCC_CSIPHY0_CLK>,388 <&camcc CAMCC_CSI0PHYTIMER_CLK>,389 <&camcc CAMCC_CSIPHY1_CLK>,390 <&camcc CAMCC_CSI1PHYTIMER_CLK>,391 <&camcc CAMCC_CSIPHY2_CLK>,392 <&camcc CAMCC_CSI2PHYTIMER_CLK>,393 <&camcc CAMCC_CSIPHY3_CLK>,394 <&camcc CAMCC_CSI3PHYTIMER_CLK>,395 <&camcc CAMCC_IFE_0_AXI_CLK>,396 <&camcc CAMCC_IFE_0_CLK>,397 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,398 <&camcc CAMCC_IFE_0_CSID_CLK>,399 <&camcc CAMCC_IFE_1_AXI_CLK>,400 <&camcc CAMCC_IFE_1_CLK>,401 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,402 <&camcc CAMCC_IFE_1_CSID_CLK>,403 <&camcc CAMCC_IFE_2_AXI_CLK>,404 <&camcc CAMCC_IFE_2_CLK>,405 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,406 <&camcc CAMCC_IFE_2_CSID_CLK>,407 <&camcc CAMCC_IFE_3_AXI_CLK>,408 <&camcc CAMCC_IFE_3_CLK>,409 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,410 <&camcc CAMCC_IFE_3_CSID_CLK>,411 <&camcc CAMCC_IFE_LITE_0_CLK>,412 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,413 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,414 <&camcc CAMCC_IFE_LITE_1_CLK>,415 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,416 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,417 <&camcc CAMCC_IFE_LITE_2_CLK>,418 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,419 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,420 <&camcc CAMCC_IFE_LITE_3_CLK>,421 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,422 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,423 <&gcc GCC_CAMERA_HF_AXI_CLK>,424 <&gcc GCC_CAMERA_SF_AXI_CLK>;425 426 clock-names = "camnoc_axi",427 "cpas_ahb",428 "csiphy0",429 "csiphy0_timer",430 "csiphy1",431 "csiphy1_timer",432 "csiphy2",433 "csiphy2_timer",434 "csiphy3",435 "csiphy3_timer",436 "vfe0_axi",437 "vfe0",438 "vfe0_cphy_rx",439 "vfe0_csid",440 "vfe1_axi",441 "vfe1",442 "vfe1_cphy_rx",443 "vfe1_csid",444 "vfe2_axi",445 "vfe2",446 "vfe2_cphy_rx",447 "vfe2_csid",448 "vfe3_axi",449 "vfe3",450 "vfe3_cphy_rx",451 "vfe3_csid",452 "vfe_lite0",453 "vfe_lite0_cphy_rx",454 "vfe_lite0_csid",455 "vfe_lite1",456 "vfe_lite1_cphy_rx",457 "vfe_lite1_csid",458 "vfe_lite2",459 "vfe_lite2_cphy_rx",460 "vfe_lite2_csid",461 "vfe_lite3",462 "vfe_lite3_cphy_rx",463 "vfe_lite3_csid",464 "gcc_axi_hf",465 "gcc_axi_sf";466 467 468 iommus = <&apps_smmu 0x2000 0x4e0>,469 <&apps_smmu 0x2020 0x4e0>,470 <&apps_smmu 0x2040 0x4e0>,471 <&apps_smmu 0x2060 0x4e0>,472 <&apps_smmu 0x2080 0x4e0>,473 <&apps_smmu 0x20e0 0x4e0>,474 <&apps_smmu 0x20c0 0x4e0>,475 <&apps_smmu 0x20a0 0x4e0>,476 <&apps_smmu 0x2400 0x4e0>,477 <&apps_smmu 0x2420 0x4e0>,478 <&apps_smmu 0x2440 0x4e0>,479 <&apps_smmu 0x2460 0x4e0>,480 <&apps_smmu 0x2480 0x4e0>,481 <&apps_smmu 0x24e0 0x4e0>,482 <&apps_smmu 0x24c0 0x4e0>,483 <&apps_smmu 0x24a0 0x4e0>;484 485 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,486 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,487 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,488 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;489 interconnect-names = "cam_ahb",490 "cam_hf_mnoc",491 "cam_sf_mnoc",492 "cam_sf_icp_mnoc";493 494 ports {495 #address-cells = <1>;496 #size-cells = <0>;497 498 port@0 {499 reg = <0>;500 #address-cells = <1>;501 #size-cells = <0>;502 503 csiphy_ep0: endpoint@0 {504 reg = <0>;505 clock-lanes = <7>;506 data-lanes = <0 1>;507 remote-endpoint = <&sensor_ep>;508 };509 };510 };511 };512 };513