361 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 3%YAML 1.24---5$id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Qualcomm CAMSS ISP9 10maintainers:11 - Robert Foss <robert.foss@linaro.org>12 13description: |14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms15 16properties:17 compatible:18 const: qcom,sdm845-camss19 20 clocks:21 minItems: 3622 maxItems: 3623 24 clock-names:25 items:26 - const: camnoc_axi27 - const: cpas_ahb28 - const: cphy_rx_src29 - const: csi030 - const: csi0_src31 - const: csi132 - const: csi1_src33 - const: csi234 - const: csi2_src35 - const: csiphy036 - const: csiphy0_timer37 - const: csiphy0_timer_src38 - const: csiphy139 - const: csiphy1_timer40 - const: csiphy1_timer_src41 - const: csiphy242 - const: csiphy2_timer43 - const: csiphy2_timer_src44 - const: csiphy345 - const: csiphy3_timer46 - const: csiphy3_timer_src47 - const: gcc_camera_ahb48 - const: gcc_camera_axi49 - const: slow_ahb_src50 - const: soc_ahb51 - const: vfe0_axi52 - const: vfe053 - const: vfe0_cphy_rx54 - const: vfe0_src55 - const: vfe1_axi56 - const: vfe157 - const: vfe1_cphy_rx58 - const: vfe1_src59 - const: vfe_lite60 - const: vfe_lite_cphy_rx61 - const: vfe_lite_src62 63 interrupts:64 minItems: 1065 maxItems: 1066 67 interrupt-names:68 items:69 - const: csid070 - const: csid171 - const: csid272 - const: csiphy073 - const: csiphy174 - const: csiphy275 - const: csiphy376 - const: vfe077 - const: vfe178 - const: vfe_lite79 80 iommus:81 maxItems: 482 83 power-domains:84 items:85 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.86 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.87 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.88 89 ports:90 $ref: /schemas/graph.yaml#/properties/ports91 92 description:93 CSI input ports.94 95 properties:96 port@0:97 $ref: /schemas/graph.yaml#/$defs/port-base98 unevaluatedProperties: false99 description:100 Input port for receiving CSI data.101 102 properties:103 endpoint:104 $ref: video-interfaces.yaml#105 unevaluatedProperties: false106 107 properties:108 data-lanes:109 minItems: 1110 maxItems: 4111 112 required:113 - data-lanes114 115 port@1:116 $ref: /schemas/graph.yaml#/$defs/port-base117 unevaluatedProperties: false118 description:119 Input port for receiving CSI data.120 121 properties:122 endpoint:123 $ref: video-interfaces.yaml#124 unevaluatedProperties: false125 126 properties:127 data-lanes:128 minItems: 1129 maxItems: 4130 131 required:132 - data-lanes133 134 port@2:135 $ref: /schemas/graph.yaml#/$defs/port-base136 unevaluatedProperties: false137 description:138 Input port for receiving CSI data.139 140 properties:141 endpoint:142 $ref: video-interfaces.yaml#143 unevaluatedProperties: false144 145 properties:146 data-lanes:147 minItems: 1148 maxItems: 4149 150 required:151 - data-lanes152 153 port@3:154 $ref: /schemas/graph.yaml#/$defs/port-base155 unevaluatedProperties: false156 description:157 Input port for receiving CSI data.158 159 properties:160 endpoint:161 $ref: video-interfaces.yaml#162 unevaluatedProperties: false163 164 properties:165 data-lanes:166 minItems: 1167 maxItems: 4168 169 required:170 - data-lanes171 172 reg:173 minItems: 10174 maxItems: 10175 176 reg-names:177 items:178 - const: csid0179 - const: csid1180 - const: csid2181 - const: csiphy0182 - const: csiphy1183 - const: csiphy2184 - const: csiphy3185 - const: vfe0186 - const: vfe1187 - const: vfe_lite188 189 vdda-phy-supply:190 description:191 Phandle to a regulator supply to PHY core block.192 193 vdda-pll-supply:194 description:195 Phandle to 1.8V regulator supply to PHY refclk pll block.196 197required:198 - clock-names199 - clocks200 - compatible201 - interrupt-names202 - interrupts203 - iommus204 - power-domains205 - reg206 - reg-names207 - vdda-phy-supply208 - vdda-pll-supply209 210additionalProperties: false211 212examples:213 - |214 #include <dt-bindings/interrupt-controller/arm-gic.h>215 #include <dt-bindings/clock/qcom,camcc-sdm845.h>216 #include <dt-bindings/clock/qcom,gcc-sdm845.h>217 218 soc {219 #address-cells = <2>;220 #size-cells = <2>;221 222 camss: camss@acb3000 {223 compatible = "qcom,sdm845-camss";224 225 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,226 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,227 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,228 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,229 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,230 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,231 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,232 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,233 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,234 <&clock_camcc CAM_CC_CSIPHY0_CLK>,235 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,236 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,237 <&clock_camcc CAM_CC_CSIPHY1_CLK>,238 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,239 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,240 <&clock_camcc CAM_CC_CSIPHY2_CLK>,241 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,242 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,243 <&clock_camcc CAM_CC_CSIPHY3_CLK>,244 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,245 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,246 <&gcc GCC_CAMERA_AHB_CLK>,247 <&gcc GCC_CAMERA_AXI_CLK>,248 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,249 <&clock_camcc CAM_CC_SOC_AHB_CLK>,250 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,251 <&clock_camcc CAM_CC_IFE_0_CLK>,252 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,253 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,254 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,255 <&clock_camcc CAM_CC_IFE_1_CLK>,256 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,257 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,258 <&clock_camcc CAM_CC_IFE_LITE_CLK>,259 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,260 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;261 262 clock-names = "camnoc_axi",263 "cpas_ahb",264 "cphy_rx_src",265 "csi0",266 "csi0_src",267 "csi1",268 "csi1_src",269 "csi2",270 "csi2_src",271 "csiphy0",272 "csiphy0_timer",273 "csiphy0_timer_src",274 "csiphy1",275 "csiphy1_timer",276 "csiphy1_timer_src",277 "csiphy2",278 "csiphy2_timer",279 "csiphy2_timer_src",280 "csiphy3",281 "csiphy3_timer",282 "csiphy3_timer_src",283 "gcc_camera_ahb",284 "gcc_camera_axi",285 "slow_ahb_src",286 "soc_ahb",287 "vfe0_axi",288 "vfe0",289 "vfe0_cphy_rx",290 "vfe0_src",291 "vfe1_axi",292 "vfe1",293 "vfe1_cphy_rx",294 "vfe1_src",295 "vfe_lite",296 "vfe_lite_cphy_rx",297 "vfe_lite_src";298 299 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,300 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,301 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,302 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,303 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,304 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,305 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,306 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,307 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,308 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;309 310 interrupt-names = "csid0",311 "csid1",312 "csid2",313 "csiphy0",314 "csiphy1",315 "csiphy2",316 "csiphy3",317 "vfe0",318 "vfe1",319 "vfe_lite";320 321 iommus = <&apps_smmu 0x0808 0x0>,322 <&apps_smmu 0x0810 0x8>,323 <&apps_smmu 0x0c08 0x0>,324 <&apps_smmu 0x0c10 0x8>;325 326 power-domains = <&clock_camcc IFE_0_GDSC>,327 <&clock_camcc IFE_1_GDSC>,328 <&clock_camcc TITAN_TOP_GDSC>;329 330 reg = <0 0xacb3000 0 0x1000>,331 <0 0xacba000 0 0x1000>,332 <0 0xacc8000 0 0x1000>,333 <0 0xac65000 0 0x1000>,334 <0 0xac66000 0 0x1000>,335 <0 0xac67000 0 0x1000>,336 <0 0xac68000 0 0x1000>,337 <0 0xacaf000 0 0x4000>,338 <0 0xacb6000 0 0x4000>,339 <0 0xacc4000 0 0x4000>;340 341 reg-names = "csid0",342 "csid1",343 "csid2",344 "csiphy0",345 "csiphy1",346 "csiphy2",347 "csiphy3",348 "vfe0",349 "vfe1",350 "vfe_lite";351 352 vdda-phy-supply = <&vreg_l1a_0p875>;353 vdda-pll-supply = <&vreg_l26a_1p2>;354 355 ports {356 #address-cells = <1>;357 #size-cells = <0>;358 };359 };360 };361