464 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2 3%YAML 1.24---5$id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Qualcomm CAMSS ISP9 10maintainers:11 - Robert Foss <robert.foss@linaro.org>12 13description: |14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.15 16properties:17 compatible:18 const: qcom,sm8250-camss19 20 clocks:21 minItems: 3722 maxItems: 3723 24 clock-names:25 items:26 - const: cam_ahb_clk27 - const: cam_hf_axi28 - const: cam_sf_axi29 - const: camnoc_axi30 - const: camnoc_axi_src31 - const: core_ahb32 - const: cpas_ahb33 - const: csiphy034 - const: csiphy0_timer35 - const: csiphy136 - const: csiphy1_timer37 - const: csiphy238 - const: csiphy2_timer39 - const: csiphy340 - const: csiphy3_timer41 - const: csiphy442 - const: csiphy4_timer43 - const: csiphy544 - const: csiphy5_timer45 - const: slow_ahb_src46 - const: vfe0_ahb47 - const: vfe0_axi48 - const: vfe049 - const: vfe0_cphy_rx50 - const: vfe0_csid51 - const: vfe0_areg52 - const: vfe1_ahb53 - const: vfe1_axi54 - const: vfe155 - const: vfe1_cphy_rx56 - const: vfe1_csid57 - const: vfe1_areg58 - const: vfe_lite_ahb59 - const: vfe_lite_axi60 - const: vfe_lite61 - const: vfe_lite_cphy_rx62 - const: vfe_lite_csid63 64 interrupts:65 minItems: 1466 maxItems: 1467 68 interrupt-names:69 items:70 - const: csiphy071 - const: csiphy172 - const: csiphy273 - const: csiphy374 - const: csiphy475 - const: csiphy576 - const: csid077 - const: csid178 - const: csid279 - const: csid380 - const: vfe081 - const: vfe182 - const: vfe_lite083 - const: vfe_lite184 85 iommus:86 minItems: 887 maxItems: 888 89 interconnects:90 minItems: 491 maxItems: 492 93 interconnect-names:94 items:95 - const: cam_ahb96 - const: cam_hf_0_mnoc97 - const: cam_sf_0_mnoc98 - const: cam_sf_icp_mnoc99 100 power-domains:101 items:102 - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.103 - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.104 - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.105 106 ports:107 $ref: /schemas/graph.yaml#/properties/ports108 109 description:110 CSI input ports.111 112 properties:113 port@0:114 $ref: /schemas/graph.yaml#/$defs/port-base115 unevaluatedProperties: false116 description:117 Input port for receiving CSI data.118 119 properties:120 endpoint:121 $ref: video-interfaces.yaml#122 unevaluatedProperties: false123 124 properties:125 clock-lanes:126 maxItems: 1127 128 data-lanes:129 minItems: 1130 maxItems: 4131 132 required:133 - clock-lanes134 - data-lanes135 136 port@1:137 $ref: /schemas/graph.yaml#/$defs/port-base138 unevaluatedProperties: false139 description:140 Input port for receiving CSI data.141 142 properties:143 endpoint:144 $ref: video-interfaces.yaml#145 unevaluatedProperties: false146 147 properties:148 clock-lanes:149 maxItems: 1150 151 data-lanes:152 minItems: 1153 maxItems: 4154 155 required:156 - clock-lanes157 - data-lanes158 159 port@2:160 $ref: /schemas/graph.yaml#/$defs/port-base161 unevaluatedProperties: false162 description:163 Input port for receiving CSI data.164 165 properties:166 endpoint:167 $ref: video-interfaces.yaml#168 unevaluatedProperties: false169 170 properties:171 clock-lanes:172 maxItems: 1173 174 data-lanes:175 minItems: 1176 maxItems: 4177 178 required:179 - clock-lanes180 - data-lanes181 182 port@3:183 $ref: /schemas/graph.yaml#/$defs/port-base184 unevaluatedProperties: false185 description:186 Input port for receiving CSI data.187 188 properties:189 endpoint:190 $ref: video-interfaces.yaml#191 unevaluatedProperties: false192 193 properties:194 clock-lanes:195 maxItems: 1196 197 data-lanes:198 minItems: 1199 maxItems: 4200 201 required:202 - clock-lanes203 - data-lanes204 205 port@4:206 $ref: /schemas/graph.yaml#/$defs/port-base207 unevaluatedProperties: false208 description:209 Input port for receiving CSI data.210 211 properties:212 endpoint:213 $ref: video-interfaces.yaml#214 unevaluatedProperties: false215 216 properties:217 clock-lanes:218 maxItems: 1219 220 data-lanes:221 minItems: 1222 maxItems: 4223 224 required:225 - clock-lanes226 - data-lanes227 228 port@5:229 $ref: /schemas/graph.yaml#/$defs/port-base230 unevaluatedProperties: false231 description:232 Input port for receiving CSI data.233 234 properties:235 endpoint:236 $ref: video-interfaces.yaml#237 unevaluatedProperties: false238 239 properties:240 clock-lanes:241 maxItems: 1242 243 data-lanes:244 minItems: 1245 maxItems: 4246 247 required:248 - clock-lanes249 - data-lanes250 251 reg:252 minItems: 10253 maxItems: 10254 255 reg-names:256 items:257 - const: csiphy0258 - const: csiphy1259 - const: csiphy2260 - const: csiphy3261 - const: csiphy4262 - const: csiphy5263 - const: vfe0264 - const: vfe1265 - const: vfe_lite0266 - const: vfe_lite1267 268 vdda-phy-supply:269 description:270 Phandle to a regulator supply to PHY core block.271 272 vdda-pll-supply:273 description:274 Phandle to 1.8V regulator supply to PHY refclk pll block.275 276required:277 - clock-names278 - clocks279 - compatible280 - interconnects281 - interconnect-names282 - interrupts283 - interrupt-names284 - iommus285 - power-domains286 - reg287 - reg-names288 - vdda-phy-supply289 - vdda-pll-supply290 291additionalProperties: false292 293examples:294 - |295 #include <dt-bindings/interrupt-controller/arm-gic.h>296 #include <dt-bindings/clock/qcom,camcc-sm8250.h>297 #include <dt-bindings/interconnect/qcom,sm8250.h>298 #include <dt-bindings/clock/qcom,gcc-sm8250.h>299 #include <dt-bindings/power/qcom-rpmpd.h>300 301 soc {302 #address-cells = <2>;303 #size-cells = <2>;304 305 camss: camss@ac6a000 {306 compatible = "qcom,sm8250-camss";307 308 reg = <0 0xac6a000 0 0x2000>,309 <0 0xac6c000 0 0x2000>,310 <0 0xac6e000 0 0x1000>,311 <0 0xac70000 0 0x1000>,312 <0 0xac72000 0 0x1000>,313 <0 0xac74000 0 0x1000>,314 <0 0xacb4000 0 0xd000>,315 <0 0xacc3000 0 0xd000>,316 <0 0xacd9000 0 0x2200>,317 <0 0xacdb200 0 0x2200>;318 reg-names = "csiphy0",319 "csiphy1",320 "csiphy2",321 "csiphy3",322 "csiphy4",323 "csiphy5",324 "vfe0",325 "vfe1",326 "vfe_lite0",327 "vfe_lite1";328 329 vdda-phy-supply = <&vreg_l5a_0p88>;330 vdda-pll-supply = <&vreg_l9a_1p2>;331 332 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,333 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,334 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,335 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,336 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,337 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,338 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,339 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,340 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,341 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,342 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,343 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,344 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,345 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;346 interrupt-names = "csiphy0",347 "csiphy1",348 "csiphy2",349 "csiphy3",350 "csiphy4",351 "csiphy5",352 "csid0",353 "csid1",354 "csid2",355 "csid3",356 "vfe0",357 "vfe1",358 "vfe_lite0",359 "vfe_lite1";360 361 power-domains = <&camcc IFE_0_GDSC>,362 <&camcc IFE_1_GDSC>,363 <&camcc TITAN_TOP_GDSC>;364 365 clocks = <&gcc GCC_CAMERA_AHB_CLK>,366 <&gcc GCC_CAMERA_HF_AXI_CLK>,367 <&gcc GCC_CAMERA_SF_AXI_CLK>,368 <&camcc CAM_CC_CAMNOC_AXI_CLK>,369 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,370 <&camcc CAM_CC_CORE_AHB_CLK>,371 <&camcc CAM_CC_CPAS_AHB_CLK>,372 <&camcc CAM_CC_CSIPHY0_CLK>,373 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,374 <&camcc CAM_CC_CSIPHY1_CLK>,375 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,376 <&camcc CAM_CC_CSIPHY2_CLK>,377 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,378 <&camcc CAM_CC_CSIPHY3_CLK>,379 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,380 <&camcc CAM_CC_CSIPHY4_CLK>,381 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,382 <&camcc CAM_CC_CSIPHY5_CLK>,383 <&camcc CAM_CC_CSI5PHYTIMER_CLK>,384 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,385 <&camcc CAM_CC_IFE_0_AHB_CLK>,386 <&camcc CAM_CC_IFE_0_AXI_CLK>,387 <&camcc CAM_CC_IFE_0_CLK>,388 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,389 <&camcc CAM_CC_IFE_0_CSID_CLK>,390 <&camcc CAM_CC_IFE_0_AREG_CLK>,391 <&camcc CAM_CC_IFE_1_AHB_CLK>,392 <&camcc CAM_CC_IFE_1_AXI_CLK>,393 <&camcc CAM_CC_IFE_1_CLK>,394 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,395 <&camcc CAM_CC_IFE_1_CSID_CLK>,396 <&camcc CAM_CC_IFE_1_AREG_CLK>,397 <&camcc CAM_CC_IFE_LITE_AHB_CLK>,398 <&camcc CAM_CC_IFE_LITE_AXI_CLK>,399 <&camcc CAM_CC_IFE_LITE_CLK>,400 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,401 <&camcc CAM_CC_IFE_LITE_CSID_CLK>;402 clock-names = "cam_ahb_clk",403 "cam_hf_axi",404 "cam_sf_axi",405 "camnoc_axi",406 "camnoc_axi_src",407 "core_ahb",408 "cpas_ahb",409 "csiphy0",410 "csiphy0_timer",411 "csiphy1",412 "csiphy1_timer",413 "csiphy2",414 "csiphy2_timer",415 "csiphy3",416 "csiphy3_timer",417 "csiphy4",418 "csiphy4_timer",419 "csiphy5",420 "csiphy5_timer",421 "slow_ahb_src",422 "vfe0_ahb",423 "vfe0_axi",424 "vfe0",425 "vfe0_cphy_rx",426 "vfe0_csid",427 "vfe0_areg",428 "vfe1_ahb",429 "vfe1_axi",430 "vfe1",431 "vfe1_cphy_rx",432 "vfe1_csid",433 "vfe1_areg",434 "vfe_lite_ahb",435 "vfe_lite_axi",436 "vfe_lite",437 "vfe_lite_cphy_rx",438 "vfe_lite_csid";439 440 iommus = <&apps_smmu 0x800 0x400>,441 <&apps_smmu 0x801 0x400>,442 <&apps_smmu 0x840 0x400>,443 <&apps_smmu 0x841 0x400>,444 <&apps_smmu 0xC00 0x400>,445 <&apps_smmu 0xC01 0x400>,446 <&apps_smmu 0xC40 0x400>,447 <&apps_smmu 0xC41 0x400>;448 449 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>,450 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>,451 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>,452 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>;453 interconnect-names = "cam_ahb",454 "cam_hf_0_mnoc",455 "cam_sf_0_mnoc",456 "cam_sf_icp_mnoc";457 458 ports {459 #address-cells = <1>;460 #size-cells = <0>;461 };462 };463 };464