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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas R-Car Fine Display Processor (FDP1)8 9maintainers:10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>11 12description:13 The FDP1 is a de-interlacing module which converts interlaced video to14 progressive video. It is capable of performing pixel format conversion15 between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are16 supported as an input to the module.17 18properties:19 compatible:20 enum:21 - renesas,fdp122 23 reg:24 maxItems: 125 26 interrupts:27 maxItems: 128 29 clocks:30 maxItems: 131 32 power-domains:33 maxItems: 134 35 resets:36 maxItems: 137 38 renesas,fcp:39 $ref: /schemas/types.yaml#/definitions/phandle40 description:41 A phandle referencing the FCP that handles memory accesses for the FDP1.42 Not allowed on R-Car Gen2, mandatory on R-Car Gen3.43 44required:45 - compatible46 - reg47 - interrupts48 - clocks49 - power-domains50 - resets51 52additionalProperties: false53 54examples:55 - |56 #include <dt-bindings/clock/renesas-cpg-mssr.h>57 #include <dt-bindings/interrupt-controller/arm-gic.h>58 #include <dt-bindings/power/r8a7795-sysc.h>59 60 fdp1@fe940000 {61 compatible = "renesas,fdp1";62 reg = <0xfe940000 0x2400>;63 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;64 clocks = <&cpg CPG_MOD 119>;65 power-domains = <&sysc R8A7795_PD_A3VP>;66 resets = <&cpg 119>;67 renesas,fcp = <&fcpf0>;68 };69...70