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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright (C) 2022 Renesas Electronics Corp.3%YAML 1.24---5$id: http://devicetree.org/schemas/media/renesas,rzg2l-cru.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Renesas RZ/G2L (and alike SoC's) Camera Data Receiving Unit (CRU) Image processing9 10maintainers:11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>12 13description:14 The CRU image processing module is a data conversion module equipped with pixel15 color space conversion, LUT, pixel format conversion, etc. An MIPI CSI-2 input and16 parallel (including ITU-R BT.656) input are provided as the image sensor interface.17 18properties:19 compatible:20 items:21 - enum:22 - renesas,r9a07g043-cru # RZ/G2UL23 - renesas,r9a07g044-cru # RZ/G2{L,LC}24 - renesas,r9a07g054-cru # RZ/V2L25 - const: renesas,rzg2l-cru26 27 reg:28 maxItems: 129 30 interrupts:31 maxItems: 332 33 interrupt-names:34 items:35 - const: image_conv36 - const: image_conv_err37 - const: axi_mst_err38 39 clocks:40 items:41 - description: CRU Main clock42 - description: CRU Register access clock43 - description: CRU image transfer clock44 45 clock-names:46 items:47 - const: video48 - const: apb49 - const: axi50 51 power-domains:52 maxItems: 153 54 resets:55 items:56 - description: CRU_PRESETN reset terminal57 - description: CRU_ARESETN reset terminal58 59 reset-names:60 items:61 - const: presetn62 - const: aresetn63 64 ports:65 $ref: /schemas/graph.yaml#/properties/ports66 67 properties:68 port@0:69 $ref: /schemas/graph.yaml#/$defs/port-base70 unevaluatedProperties: false71 description:72 Input port node, single endpoint describing a parallel input source.73 74 properties:75 endpoint:76 $ref: video-interfaces.yaml#77 unevaluatedProperties: false78 79 properties:80 hsync-active: true81 vsync-active: true82 bus-width: true83 data-shift: true84 85 port@1:86 $ref: /schemas/graph.yaml#/properties/port87 description:88 Input port node, describing the Image Processing module connected to the89 CSI-2 receiver.90 91required:92 - compatible93 - reg94 - interrupts95 - interrupt-names96 - clocks97 - clock-names98 - resets99 - reset-names100 - power-domains101 102allOf:103 - if:104 properties:105 compatible:106 contains:107 enum:108 - renesas,r9a07g044-cru109 - renesas,r9a07g054-cru110 then:111 properties:112 ports:113 required:114 - port@0115 - port@1116 117 - if:118 properties:119 compatible:120 contains:121 enum:122 - renesas,r9a07g043-cru123 then:124 properties:125 ports:126 properties:127 port@0: false128 129 required:130 - port@1131 132additionalProperties: false133 134examples:135 # Device node example with CSI-2136 - |137 #include <dt-bindings/clock/r9a07g044-cpg.h>138 #include <dt-bindings/interrupt-controller/arm-gic.h>139 140 cru: video@10830000 {141 compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";142 reg = <0x10830000 0x400>;143 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,144 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,145 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;146 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";147 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,148 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,149 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;150 clock-names = "video", "apb", "axi";151 power-domains = <&cpg>;152 resets = <&cpg R9A07G044_CRU_PRESETN>,153 <&cpg R9A07G044_CRU_ARESETN>;154 reset-names = "presetn", "aresetn";155 156 ports {157 #address-cells = <1>;158 #size-cells = <0>;159 160 port@0 {161 #address-cells = <1>;162 #size-cells = <0>;163 reg = <0>;164 165 cru_parallel_in: endpoint@0 {166 reg = <0>;167 remote-endpoint = <&ov5642>;168 hsync-active = <1>;169 vsync-active = <1>;170 };171 };172 173 port@1 {174 #address-cells = <1>;175 #size-cells = <0>;176 reg = <1>;177 178 cru_csi_in: endpoint@0 {179 reg = <0>;180 remote-endpoint = <&csi_cru_in>;181 };182 };183 };184 };185