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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2# Copyright (C) 2022 Renesas Electronics Corp.3%YAML 1.24---5$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver9 10maintainers:11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>12 13description:14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction16 with the Image Processing module, which provides the video capture capabilities.17 18properties:19 compatible:20 items:21 - enum:22 - renesas,r9a07g043-csi2 # RZ/G2UL23 - renesas,r9a07g044-csi2 # RZ/G2{L,LC}24 - renesas,r9a07g054-csi2 # RZ/V2L25 - const: renesas,rzg2l-csi226 27 reg:28 maxItems: 129 30 interrupts:31 maxItems: 132 33 clocks:34 items:35 - description: Internal clock for connecting CRU and MIPI36 - description: CRU Main clock37 - description: CRU Register access clock38 39 clock-names:40 items:41 - const: system42 - const: video43 - const: apb44 45 power-domains:46 maxItems: 147 48 resets:49 items:50 - description: CRU_PRESETN reset terminal51 - description: CRU_CMN_RSTB reset terminal52 53 reset-names:54 items:55 - const: presetn56 - const: cmn-rstb57 58 ports:59 $ref: /schemas/graph.yaml#/properties/ports60 61 properties:62 port@0:63 $ref: /schemas/graph.yaml#/$defs/port-base64 unevaluatedProperties: false65 description:66 Input port node, single endpoint describing the CSI-2 transmitter.67 68 properties:69 endpoint:70 $ref: video-interfaces.yaml#71 unevaluatedProperties: false72 73 properties:74 data-lanes:75 minItems: 176 maxItems: 477 items:78 maximum: 479 80 required:81 - clock-lanes82 - data-lanes83 84 port@1:85 $ref: /schemas/graph.yaml#/properties/port86 description:87 Output port node, Image Processing block connected to the CSI-2 receiver.88 89 required:90 - port@091 - port@192 93required:94 - compatible95 - reg96 - interrupts97 - clocks98 - clock-names99 - power-domains100 - resets101 - reset-names102 - ports103 104additionalProperties: false105 106examples:107 - |108 #include <dt-bindings/clock/r9a07g044-cpg.h>109 #include <dt-bindings/interrupt-controller/arm-gic.h>110 111 csi: csi@10830400 {112 compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";113 reg = <0x10830400 0xfc00>;114 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;115 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,116 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,117 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;118 clock-names = "system", "video", "apb";119 power-domains = <&cpg>;120 resets = <&cpg R9A07G044_CRU_PRESETN>,121 <&cpg R9A07G044_CRU_CMN_RSTB>;122 reset-names = "presetn", "cmn-rstb";123 124 ports {125 #address-cells = <1>;126 #size-cells = <0>;127 128 port@0 {129 reg = <0>;130 131 csi2_in: endpoint {132 clock-lanes = <0>;133 data-lanes = <1 2>;134 remote-endpoint = <&ov5645_ep>;135 };136 };137 138 port@1 {139 #address-cells = <1>;140 #size-cells = <0>;141 142 reg = <1>;143 144 csi2cru: endpoint@0 {145 reg = <0>;146 remote-endpoint = <&crucsi2>;147 };148 };149 };150 };151