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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Renesas VSP Video Processing Engine8 9maintainers:10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>11 12description:13 The VSP is a video processing engine that supports up-/down-scaling, alpha14 blending, color space conversion and various other image processing features.15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.16 17properties:18 compatible:19 oneOf:20 - enum:21 - renesas,r9a07g044-vsp2 # RZ/G2L22 - renesas,vsp1 # R-Car Gen2 and RZ/G123 - renesas,vsp2 # R-Car Gen3 and RZ/G224 - items:25 - enum:26 - renesas,r9a07g043u-vsp2 # RZ/G2UL27 - renesas,r9a07g054-vsp2 # RZ/V2L28 - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback29 30 reg:31 maxItems: 132 33 interrupts:34 maxItems: 135 36 clocks: true37 clock-names: true38 39 power-domains:40 maxItems: 141 42 resets:43 maxItems: 144 45 renesas,fcp:46 $ref: /schemas/types.yaml#/definitions/phandle47 description:48 A phandle referencing the FCP that handles memory accesses for the VSP.49 50required:51 - compatible52 - reg53 - interrupts54 - clocks55 - power-domains56 - resets57 58additionalProperties: false59 60allOf:61 - if:62 properties:63 compatible:64 contains:65 const: renesas,vsp166 then:67 properties:68 renesas,fcp: false69 else:70 required:71 - renesas,fcp72 73 - if:74 properties:75 compatible:76 contains:77 const: renesas,r9a07g044-vsp278 then:79 properties:80 clocks:81 items:82 - description: Main clock83 - description: Register access clock84 - description: Video clock85 clock-names:86 items:87 - const: aclk88 - const: pclk89 - const: vclk90 required:91 - clock-names92 else:93 properties:94 clocks:95 maxItems: 196 clock-names: false97 98examples:99 # R8A7790 (R-Car H2) VSP1-S100 - |101 #include <dt-bindings/clock/renesas-cpg-mssr.h>102 #include <dt-bindings/interrupt-controller/arm-gic.h>103 #include <dt-bindings/power/r8a7790-sysc.h>104 105 vsp@fe928000 {106 compatible = "renesas,vsp1";107 reg = <0xfe928000 0x8000>;108 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;109 clocks = <&cpg CPG_MOD 131>;110 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;111 resets = <&cpg 131>;112 };113 114 # R8A77951 (R-Car H3) VSP2-BC115 - |116 #include <dt-bindings/clock/renesas-cpg-mssr.h>117 #include <dt-bindings/interrupt-controller/arm-gic.h>118 #include <dt-bindings/power/r8a7795-sysc.h>119 120 vsp@fe920000 {121 compatible = "renesas,vsp2";122 reg = <0xfe920000 0x8000>;123 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;124 clocks = <&cpg CPG_MOD 624>;125 power-domains = <&sysc R8A7795_PD_A3VP>;126 resets = <&cpg 624>;127 128 renesas,fcp = <&fcpvb1>;129 };130...131