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1* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller2 3Required properties:4 5- compatible: Must be "arm,primecell" and exactly one from6 "arm,pl172", "arm,pl175" or "arm,pl176".7 8- reg: Must contains offset/length value for controller.9 10- #address-cells: Must be 2. The partition number has to be encoded in the11 first address cell and it may accept values 0..N-112 (N - total number of partitions). The second cell is the13 offset into the partition.14 15- #size-cells: Must be set to 1.16 17- ranges: Must contain one or more chip select memory regions.18 19- clocks: Must contain references to controller clocks.20 21- clock-names: Must contain "mpmcclk" and "apb_pclk".22 23- clock-ranges: Empty property indicating that child nodes can inherit24 named clocks. Required only if clock tree data present25 in device tree.26 See clock-bindings.txt27 28Child chip-select (cs) nodes contain the memory devices nodes connected to29such as NOR (e.g. cfi-flash) and NAND.30 31Required child cs node properties:32 33- #address-cells: Must be 2.34 35- #size-cells: Must be 1.36 37- ranges: Empty property indicating that child nodes can inherit38 memory layout.39 40- clock-ranges: Empty property indicating that child nodes can inherit41 named clocks. Required only if clock tree data present42 in device tree.43 44- mpmc,cs: Chip select number. Indicates to the pl0172 driver45 which chipselect is used for accessing the memory.46 47- mpmc,memory-width: Width of the chip select memory. Must be equal to48 either 8, 16 or 32.49 50Optional child cs node config properties:51 52- mpmc,async-page-mode: Enable asynchronous page mode.53 54- mpmc,cs-active-high: Set chip select polarity to active high.55 56- mpmc,byte-lane-low: Set byte lane state to low.57 58- mpmc,extended-wait: Enable extended wait.59 60- mpmc,buffer-enable: Enable write buffer, option is not supported by61 PL175 and PL176 controllers.62 63- mpmc,write-protect: Enable write protect.64 65Optional child cs node timing properties:66 67- mpmc,write-enable-delay: Delay from chip select assertion to write68 enable (WE signal) in nano seconds.69 70- mpmc,output-enable-delay: Delay from chip select assertion to output71 enable (OE signal) in nano seconds.72 73- mpmc,write-access-delay: Delay from chip select assertion to write74 access in nano seconds.75 76- mpmc,read-access-delay: Delay from chip select assertion to read77 access in nano seconds.78 79- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential80 accesses in nano seconds.81 82- mpmc,turn-round-delay: Delay between access to memory banks in nano83 seconds.84 85If any of the above timing parameters are absent, current parameter value will86be taken from the corresponding HW reg.87 88Example for pl172 with nor flash on chip select 0 shown below.89 90emc: memory-controller@40005000 {91 compatible = "arm,pl172", "arm,primecell";92 reg = <0x40005000 0x1000>;93 clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;94 clock-names = "mpmcclk", "apb_pclk";95 #address-cells = <2>;96 #size-cells = <1>;97 ranges = <0 0 0x1c000000 0x100000098 1 0 0x1d000000 0x100000099 2 0 0x1e000000 0x1000000100 3 0 0x1f000000 0x1000000>;101 102 cs0 {103 #address-cells = <2>;104 #size-cells = <1>;105 ranges;106 107 mpmc,cs = <0>;108 mpmc,memory-width = <16>;109 mpmc,byte-lane-low;110 mpmc,write-enable-delay = <0>;111 mpmc,output-enable-delay = <0>;112 mpmc,read-enable-delay = <70>;113 mpmc,page-mode-read-delay = <70>;114 115 flash@0,0 {116 compatible = "sst,sst39vf320", "cfi-flash";117 reg = <0 0 0x400000>;118 bank-width = <2>;119 #address-cells = <1>;120 #size-cells = <1>;121 partition@0 {122 label = "data";123 reg = <0 0x400000>;124 };125 };126 };127};128