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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Arm PL35x Series Static Memory Controller (SMC)8 9maintainers:10 - Miquel Raynal <miquel.raynal@bootlin.com>11 12description: |13 The PL35x Static Memory Controller is a bus where you can connect two kinds14 of memory interfaces, which are NAND and memory mapped interfaces (such as15 SRAM or NOR) depending on the specific configuration.16 17 The TRM is available here:18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa19 20# We need a select here so we don't match all nodes with 'arm,primecell'21select:22 properties:23 compatible:24 contains:25 enum:26 - arm,pl353-smc-r2p127 - arm,pl35428 required:29 - compatible30 31properties:32 $nodename:33 pattern: "^memory-controller@[0-9a-f]+$"34 35 compatible:36 items:37 - enum:38 - arm,pl353-smc-r2p139 - arm,pl35440 - const: arm,primecell41 42 "#address-cells":43 const: 244 45 "#size-cells":46 const: 147 48 reg:49 items:50 - description:51 Configuration registers for the host and sub-controllers.52 The three chip select regions are defined in 'ranges'.53 54 clocks:55 minItems: 156 maxItems: 257 58 clock-names:59 minItems: 160 maxItems: 261 62 ranges:63 minItems: 164 maxItems: 865 66 interrupts:67 minItems: 168 items:69 - description: Combined or Memory interface 0 IRQ70 - description: Memory interface 1 IRQ71 72patternProperties:73 "@[0-7],[a-f0-9]+$":74 type: object75 additionalProperties: true76 description: |77 The child device node represents the controller connected to the SMC78 bus. The controller can be a NAND controller or a pair of any memory79 mapped controllers such as NOR and SRAM controllers.80 81 properties:82 compatible:83 description:84 Compatible of memory controller.85 86 reg:87 items:88 - items:89 - description: |90 Chip-select ID, as in the parent range property.91 minimum: 092 maximum: 793 - description: |94 Offset of the memory region requested by the device.95 - description: |96 Length of the memory region requested by the device.97 98 required:99 - compatible100 - reg101 102required:103 - compatible104 - reg105 - clock-names106 - clocks107 108additionalProperties: false109 110allOf:111 - if:112 properties:113 compatible:114 contains:115 const: arm,pl354116 then:117 properties:118 clocks:119 # According to TRM, really should be 3 clocks120 maxItems: 1121 122 clock-names:123 const: apb_pclk124 125 else:126 properties:127 clocks:128 items:129 - description: clock for the memory device bus130 - description: main clock of the SMC131 132 clock-names:133 items:134 - const: memclk135 - const: apb_pclk136 137examples:138 - |139 smcc: memory-controller@e000e000 {140 compatible = "arm,pl353-smc-r2p1", "arm,primecell";141 reg = <0xe000e000 0x0001000>;142 clock-names = "memclk", "apb_pclk";143 clocks = <&clkc 11>, <&clkc 44>;144 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */145 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */146 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */147 #address-cells = <2>;148 #size-cells = <1>;149 150 nfc0: nand-controller@0,0 {151 compatible = "arm,pl353-nand-r2p1";152 reg = <0 0 0x1000000>;153 #address-cells = <1>;154 #size-cells = <0>;155 };156 };157