53 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/brcm,brcmstb-memc-ddr.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Memory controller (MEMC) for Broadcom STB8 9maintainers:10 - Florian Fainelli <f.fainelli@gmail.com>11 12properties:13 compatible:14 items:15 - enum:16 - brcm,brcmstb-memc-ddr-rev-b.1.x17 - brcm,brcmstb-memc-ddr-rev-b.2.018 - brcm,brcmstb-memc-ddr-rev-b.2.119 - brcm,brcmstb-memc-ddr-rev-b.2.220 - brcm,brcmstb-memc-ddr-rev-b.2.321 - brcm,brcmstb-memc-ddr-rev-b.2.522 - brcm,brcmstb-memc-ddr-rev-b.2.623 - brcm,brcmstb-memc-ddr-rev-b.2.724 - brcm,brcmstb-memc-ddr-rev-b.2.825 - brcm,brcmstb-memc-ddr-rev-b.3.026 - brcm,brcmstb-memc-ddr-rev-b.3.127 - brcm,brcmstb-memc-ddr-rev-c.1.028 - brcm,brcmstb-memc-ddr-rev-c.1.129 - brcm,brcmstb-memc-ddr-rev-c.1.230 - brcm,brcmstb-memc-ddr-rev-c.1.331 - brcm,brcmstb-memc-ddr-rev-c.1.432 - const: brcm,brcmstb-memc-ddr33 34 reg:35 maxItems: 136 37 clock-frequency:38 description: DDR PHY frequency in Hz39 40required:41 - compatible42 - reg43 44additionalProperties: false45 46examples:47 - |48 memory-controller@9902000 {49 compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";50 reg = <0x9902000 0x600>;51 clock-frequency = <2133000000>;52 };53