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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Common properties for LPDDR types8 9description:10 Different LPDDR types generally use the same properties and only differ in the11 range of legal values for each. This file defines the common parts that can be12 reused for each type. Nodes using this schema should generally be nested under13 an LPDDR channel node.14 15maintainers:16 - Krzysztof Kozlowski <krzk@kernel.org>17 18properties:19 compatible:20 description:21 Compatible strings can be either explicit vendor names and part numbers22 (e.g. elpida,ECB240ABACN), or generated strings of the form23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID24 (from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are25 formatted in lower case hexadecimal representation with leading zeroes.26 The latter form can be useful when LPDDR nodes are created at runtime by27 boot firmware that doesn't have access to static part number information.28 29 reg:30 description:31 The rank number of this LPDDR rank when used as a subnode to an LPDDR32 channel.33 minimum: 034 maximum: 335 36 revision-id:37 $ref: /schemas/types.yaml#/definitions/uint32-array38 description:39 Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).40 maxItems: 241 items:42 minimum: 043 maximum: 25544 45 density:46 $ref: /schemas/types.yaml#/definitions/uint3247 description:48 Density in megabits of SDRAM chip. Decoded from Mode Register 8.49 enum:50 - 6451 - 12852 - 25653 - 51254 - 102455 - 204856 - 307257 - 409658 - 614459 - 819260 - 1228861 - 1638462 - 2457663 - 3276864 65 io-width:66 $ref: /schemas/types.yaml#/definitions/uint3267 description:68 IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.69 enum:70 - 871 - 1672 - 3273 74additionalProperties: true75