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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: LPDDR3 SDRAM AC timing parameters for a given speed-bin8 9maintainers:10 - Krzysztof Kozlowski <krzk@kernel.org>11 12properties:13 compatible:14 const: jedec,lpddr3-timings15 16 reg:17 maxItems: 118 description: |19 Maximum DDR clock frequency for the speed-bin, in Hz.20 Property is deprecated, use max-freq.21 deprecated: true22 23 max-freq:24 $ref: /schemas/types.yaml#/definitions/uint3225 description: |26 Maximum DDR clock frequency for the speed-bin, in Hz.27 28 min-freq:29 $ref: /schemas/types.yaml#/definitions/uint3230 description: |31 Minimum DDR clock frequency for the speed-bin, in Hz.32 33 tCKE:34 $ref: /schemas/types.yaml#/definitions/uint3235 description: |36 CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.37 38 tCKESR:39 $ref: /schemas/types.yaml#/definitions/uint3240 description: |41 CKE minimum pulse width during SELF REFRESH (low pulse width during42 SELF REFRESH) in pico seconds.43 44 tFAW:45 $ref: /schemas/types.yaml#/definitions/uint3246 description: |47 Four-bank activate window in pico seconds.48 49 tMRD:50 $ref: /schemas/types.yaml#/definitions/uint3251 description: |52 Mode register set command delay in pico seconds.53 54 tR2R-C2C:55 $ref: /schemas/types.yaml#/definitions/uint3256 description: |57 Additional READ-to-READ delay in chip-to-chip cases in pico seconds.58 59 tRAS:60 $ref: /schemas/types.yaml#/definitions/uint3261 description: |62 Row active time in pico seconds.63 64 tRC:65 $ref: /schemas/types.yaml#/definitions/uint3266 description: |67 ACTIVATE-to-ACTIVATE command period in pico seconds.68 69 tRCD:70 $ref: /schemas/types.yaml#/definitions/uint3271 description: |72 RAS-to-CAS delay in pico seconds.73 74 tRFC:75 $ref: /schemas/types.yaml#/definitions/uint3276 description: |77 Refresh Cycle time in pico seconds.78 79 tRPab:80 $ref: /schemas/types.yaml#/definitions/uint3281 description: |82 Row precharge time (all banks) in pico seconds.83 84 tRPpb:85 $ref: /schemas/types.yaml#/definitions/uint3286 description: |87 Row precharge time (single banks) in pico seconds.88 89 tRRD:90 $ref: /schemas/types.yaml#/definitions/uint3291 description: |92 Active bank A to active bank B in pico seconds.93 94 tRTP:95 $ref: /schemas/types.yaml#/definitions/uint3296 description: |97 Internal READ to PRECHARGE command delay in pico seconds.98 99 tW2W-C2C:100 $ref: /schemas/types.yaml#/definitions/uint32101 description: |102 Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.103 104 tWR:105 $ref: /schemas/types.yaml#/definitions/uint32106 description: |107 WRITE recovery time in pico seconds.108 109 tWTR:110 $ref: /schemas/types.yaml#/definitions/uint32111 description: |112 Internal WRITE-to-READ command delay in pico seconds.113 114 tXP:115 $ref: /schemas/types.yaml#/definitions/uint32116 description: |117 Exit power-down to next valid command delay in pico seconds.118 119 tXSR:120 $ref: /schemas/types.yaml#/definitions/uint32121 description: |122 SELF REFRESH exit to next valid command delay in pico seconds.123 124required:125 - compatible126 - min-freq127 - max-freq128 129additionalProperties: false130 131examples:132 - |133 lpddr3 {134 timings {135 compatible = "jedec,lpddr3-timings";136 max-freq = <800000000>;137 min-freq = <100000000>;138 tCKE = <3750>;139 tCKESR = <3750>;140 tFAW = <25000>;141 tMRD = <7000>;142 tR2R-C2C = <0>;143 tRAS = <23000>;144 tRC = <33750>;145 tRCD = <10000>;146 tRFC = <65000>;147 tRPab = <12000>;148 tRPpb = <12000>;149 tRRD = <6000>;150 tRTP = <3750>;151 tW2W-C2C = <0>;152 tWR = <7500>;153 tWTR = <3750>;154 tXP = <3750>;155 tXSR = <70000>;156 };157 };158