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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (c) 2020 MediaTek Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: SMI (Smart Multimedia Interface) Common9 10maintainers:11 - Yong Wu <yong.wu@mediatek.com>12 13description: |14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml15 16 MediaTek SMI have two generations of HW architecture, here is the list17 which generation the SoCs use:18 generation 1: mt2701 and mt7623.19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.20 21 There's slight differences between the two SMI, for generation 2, the22 register which control the iommu port is at each larb's register base. But23 for generation 1, the register is at smi ao base(smi always on register24 base). Besides that, the smi async clock should be prepared and enabled for25 SMI generation 1 to transform the smi clock into emi clock domain, but that is26 not needed for SMI generation 2.27 28properties:29 compatible:30 oneOf:31 - enum:32 - mediatek,mt2701-smi-common33 - mediatek,mt2712-smi-common34 - mediatek,mt6779-smi-common35 - mediatek,mt6795-smi-common36 - mediatek,mt8167-smi-common37 - mediatek,mt8173-smi-common38 - mediatek,mt8183-smi-common39 - mediatek,mt8186-smi-common40 - mediatek,mt8188-smi-common-vdo41 - mediatek,mt8188-smi-common-vpp42 - mediatek,mt8192-smi-common43 - mediatek,mt8195-smi-common-vdo44 - mediatek,mt8195-smi-common-vpp45 - mediatek,mt8195-smi-sub-common46 - mediatek,mt8365-smi-common47 48 - description: for mt762349 items:50 - const: mediatek,mt7623-smi-common51 - const: mediatek,mt2701-smi-common52 53 reg:54 maxItems: 155 56 power-domains:57 maxItems: 158 59 clocks:60 description: |61 apb and smi are mandatory. the async is only for generation 1 smi HW.62 gals(global async local sync) also is optional, see below.63 minItems: 264 items:65 - description: apb is Advanced Peripheral Bus clock, It's the clock for66 setting the register.67 - description: smi is the clock for transfer data and command.68 - description: Either asynchronous clock to help transform the smi clock69 into the emi clock domain on Gen1 h/w, or the path0 clock of gals.70 - description: gals1 is the path1 clock of gals.71 72 clock-names:73 minItems: 274 maxItems: 475 76 mediatek,smi:77 $ref: /schemas/types.yaml#/definitions/phandle78 description: a phandle to the smi-common node above. Only for sub-common.79 80required:81 - compatible82 - reg83 - power-domains84 - clocks85 - clock-names86 87allOf:88 - if: # only for gen1 HW89 properties:90 compatible:91 contains:92 enum:93 - mediatek,mt2701-smi-common94 then:95 properties:96 clocks:97 minItems: 398 maxItems: 399 clock-names:100 items:101 - const: apb102 - const: smi103 - const: async104 105 - if: # only for sub common106 properties:107 compatible:108 contains:109 enum:110 - mediatek,mt8195-smi-sub-common111 then:112 required:113 - mediatek,smi114 properties:115 clocks:116 minItems: 3117 maxItems: 3118 clock-names:119 items:120 - const: apb121 - const: smi122 - const: gals0123 else:124 properties:125 mediatek,smi: false126 127 - if: # for gen2 HW that have gals128 properties:129 compatible:130 enum:131 - mediatek,mt6779-smi-common132 - mediatek,mt8183-smi-common133 - mediatek,mt8186-smi-common134 - mediatek,mt8192-smi-common135 - mediatek,mt8195-smi-common-vdo136 - mediatek,mt8195-smi-common-vpp137 - mediatek,mt8365-smi-common138 139 then:140 properties:141 clocks:142 minItems: 4143 maxItems: 4144 clock-names:145 items:146 - const: apb147 - const: smi148 - const: gals0149 - const: gals1150 151 - if: # for gen2 HW that don't have gals152 properties:153 compatible:154 enum:155 - mediatek,mt2712-smi-common156 - mediatek,mt6795-smi-common157 - mediatek,mt8167-smi-common158 - mediatek,mt8173-smi-common159 160 then:161 properties:162 clocks:163 minItems: 2164 maxItems: 2165 clock-names:166 items:167 - const: apb168 - const: smi169 170additionalProperties: false171 172examples:173 - |+174 #include <dt-bindings/clock/mt8173-clk.h>175 #include <dt-bindings/power/mt8173-power.h>176 177 smi_common: smi@14022000 {178 compatible = "mediatek,mt8173-smi-common";179 reg = <0x14022000 0x1000>;180 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;181 clocks = <&mmsys CLK_MM_SMI_COMMON>,182 <&mmsys CLK_MM_SMI_COMMON>;183 clock-names = "apb", "smi";184 };185