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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Nuvoton NPCM Memory Controller8 9maintainers:10 - Marvin Lin <kflin@nuvoton.com>11 - Stanley Chu <yschu@nuvoton.com>12 13description: |14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction15 check).16 17 The memory controller supports single bit error correction, double bit error18 detection (in-line ECC in which a section (1/8th) of the memory device used to19 store data is used for ECC storage).20 21 Note, the bootloader must configure ECC mode for the memory controller.22 23properties:24 compatible:25 enum:26 - nuvoton,npcm750-memory-controller27 - nuvoton,npcm845-memory-controller28 29 reg:30 maxItems: 131 32 interrupts:33 maxItems: 134 35required:36 - compatible37 - reg38 - interrupts39 40additionalProperties: false41 42examples:43 - |44 #include <dt-bindings/interrupt-controller/arm-gic.h>45 46 mc: memory-controller@f0824000 {47 compatible = "nuvoton,npcm750-memory-controller";48 reg = <0xf0824000 0x1000>;49 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;50 };51