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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra124 SoC External Memory Controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13description: |14 The EMC interfaces with the off-chip SDRAM to service the request stream15 sent from the memory controller.16 17properties:18 compatible:19 const: nvidia,tegra124-emc20 21 reg:22 maxItems: 123 24 clocks:25 items:26 - description: external memory clock27 28 clock-names:29 items:30 - const: emc31 32 "#interconnect-cells":33 const: 034 35 nvidia,memory-controller:36 $ref: /schemas/types.yaml#/definitions/phandle37 description:38 phandle of the memory controller node39 40 power-domains:41 maxItems: 142 description:43 Phandle of the SoC "core" power domain.44 45 operating-points-v2:46 description:47 Should contain freqs and voltages and opp-supported-hw property, which48 is a bitfield indicating SoC speedo ID mask.49 50patternProperties:51 "^emc-timings-[0-9]+$":52 type: object53 additionalProperties: false54 properties:55 nvidia,ram-code:56 $ref: /schemas/types.yaml#/definitions/uint3257 description:58 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that59 this timing set is used for60 61 patternProperties:62 "^timing-[0-9]+$":63 type: object64 properties:65 clock-frequency:66 description:67 external memory clock rate in Hz68 minimum: 100000069 maximum: 100000000070 71 nvidia,emc-auto-cal-config:72 $ref: /schemas/types.yaml#/definitions/uint3273 description:74 value of the EMC_AUTO_CAL_CONFIG register for this set of75 timings76 77 nvidia,emc-auto-cal-config2:78 $ref: /schemas/types.yaml#/definitions/uint3279 description:80 value of the EMC_AUTO_CAL_CONFIG2 register for this set of81 timings82 83 nvidia,emc-auto-cal-config3:84 $ref: /schemas/types.yaml#/definitions/uint3285 description:86 value of the EMC_AUTO_CAL_CONFIG3 register for this set of87 timings88 89 nvidia,emc-auto-cal-interval:90 description:91 pad calibration interval in microseconds92 $ref: /schemas/types.yaml#/definitions/uint3293 minimum: 094 maximum: 209715195 96 nvidia,emc-bgbias-ctl0:97 $ref: /schemas/types.yaml#/definitions/uint3298 description:99 value of the EMC_BGBIAS_CTL0 register for this set of timings100 101 nvidia,emc-cfg:102 $ref: /schemas/types.yaml#/definitions/uint32103 description:104 value of the EMC_CFG register for this set of timings105 106 nvidia,emc-cfg-2:107 $ref: /schemas/types.yaml#/definitions/uint32108 description:109 value of the EMC_CFG_2 register for this set of timings110 111 nvidia,emc-ctt-term-ctrl:112 $ref: /schemas/types.yaml#/definitions/uint32113 description:114 value of the EMC_CTT_TERM_CTRL register for this set of timings115 116 nvidia,emc-mode-1:117 $ref: /schemas/types.yaml#/definitions/uint32118 description:119 value of the EMC_MRW register for this set of timings120 121 nvidia,emc-mode-2:122 $ref: /schemas/types.yaml#/definitions/uint32123 description:124 value of the EMC_MRW2 register for this set of timings125 126 nvidia,emc-mode-4:127 $ref: /schemas/types.yaml#/definitions/uint32128 description:129 value of the EMC_MRW4 register for this set of timings130 131 nvidia,emc-mode-reset:132 $ref: /schemas/types.yaml#/definitions/uint32133 description:134 reset value of the EMC_MRS register for this set of timings135 136 nvidia,emc-mrs-wait-cnt:137 $ref: /schemas/types.yaml#/definitions/uint32138 description:139 value of the EMR_MRS_WAIT_CNT register for this set of timings140 141 nvidia,emc-sel-dpd-ctrl:142 $ref: /schemas/types.yaml#/definitions/uint32143 description:144 value of the EMC_SEL_DPD_CTRL register for this set of timings145 146 nvidia,emc-xm2dqspadctrl2:147 $ref: /schemas/types.yaml#/definitions/uint32148 description:149 value of the EMC_XM2DQSPADCTRL2 register for this set of timings150 151 nvidia,emc-zcal-cnt-long:152 description:153 number of EMC clocks to wait before issuing any commands after154 clock change155 $ref: /schemas/types.yaml#/definitions/uint32156 minimum: 0157 maximum: 1023158 159 nvidia,emc-zcal-interval:160 $ref: /schemas/types.yaml#/definitions/uint32161 description:162 value of the EMC_ZCAL_INTERVAL register for this set of timings163 164 nvidia,emc-configuration:165 description:166 EMC timing characterization data. These are the registers (see167 section "15.6.2 EMC Registers" in the TRM) whose values need to168 be specified, according to the board documentation.169 $ref: /schemas/types.yaml#/definitions/uint32-array170 items:171 - description: EMC_RC172 - description: EMC_RFC173 - description: EMC_RFC_SLR174 - description: EMC_RAS175 - description: EMC_RP176 - description: EMC_R2W177 - description: EMC_W2R178 - description: EMC_R2P179 - description: EMC_W2P180 - description: EMC_RD_RCD181 - description: EMC_WR_RCD182 - description: EMC_RRD183 - description: EMC_REXT184 - description: EMC_WEXT185 - description: EMC_WDV186 - description: EMC_WDV_MASK187 - description: EMC_QUSE188 - description: EMC_QUSE_WIDTH189 - description: EMC_IBDLY190 - description: EMC_EINPUT191 - description: EMC_EINPUT_DURATION192 - description: EMC_PUTERM_EXTRA193 - description: EMC_PUTERM_WIDTH194 - description: EMC_PUTERM_ADJ195 - description: EMC_CDB_CNTL_1196 - description: EMC_CDB_CNTL_2197 - description: EMC_CDB_CNTL_3198 - description: EMC_QRST199 - description: EMC_QSAFE200 - description: EMC_RDV201 - description: EMC_RDV_MASK202 - description: EMC_REFRESH203 - description: EMC_BURST_REFRESH_NUM204 - description: EMC_PRE_REFRESH_REQ_CNT205 - description: EMC_PDEX2WR206 - description: EMC_PDEX2RD207 - description: EMC_PCHG2PDEN208 - description: EMC_ACT2PDEN209 - description: EMC_AR2PDEN210 - description: EMC_RW2PDEN211 - description: EMC_TXSR212 - description: EMC_TXSRDLL213 - description: EMC_TCKE214 - description: EMC_TCKESR215 - description: EMC_TPD216 - description: EMC_TFAW217 - description: EMC_TRPAB218 - description: EMC_TCLKSTABLE219 - description: EMC_TCLKSTOP220 - description: EMC_TREFBW221 - description: EMC_FBIO_CFG6222 - description: EMC_ODT_WRITE223 - description: EMC_ODT_READ224 - description: EMC_FBIO_CFG5225 - description: EMC_CFG_DIG_DLL226 - description: EMC_CFG_DIG_DLL_PERIOD227 - description: EMC_DLL_XFORM_DQS0228 - description: EMC_DLL_XFORM_DQS1229 - description: EMC_DLL_XFORM_DQS2230 - description: EMC_DLL_XFORM_DQS3231 - description: EMC_DLL_XFORM_DQS4232 - description: EMC_DLL_XFORM_DQS5233 - description: EMC_DLL_XFORM_DQS6234 - description: EMC_DLL_XFORM_DQS7235 - description: EMC_DLL_XFORM_DQS8236 - description: EMC_DLL_XFORM_DQS9237 - description: EMC_DLL_XFORM_DQS10238 - description: EMC_DLL_XFORM_DQS11239 - description: EMC_DLL_XFORM_DQS12240 - description: EMC_DLL_XFORM_DQS13241 - description: EMC_DLL_XFORM_DQS14242 - description: EMC_DLL_XFORM_DQS15243 - description: EMC_DLL_XFORM_QUSE0244 - description: EMC_DLL_XFORM_QUSE1245 - description: EMC_DLL_XFORM_QUSE2246 - description: EMC_DLL_XFORM_QUSE3247 - description: EMC_DLL_XFORM_QUSE4248 - description: EMC_DLL_XFORM_QUSE5249 - description: EMC_DLL_XFORM_QUSE6250 - description: EMC_DLL_XFORM_QUSE7251 - description: EMC_DLL_XFORM_ADDR0252 - description: EMC_DLL_XFORM_ADDR1253 - description: EMC_DLL_XFORM_ADDR2254 - description: EMC_DLL_XFORM_ADDR3255 - description: EMC_DLL_XFORM_ADDR4256 - description: EMC_DLL_XFORM_ADDR5257 - description: EMC_DLL_XFORM_QUSE8258 - description: EMC_DLL_XFORM_QUSE9259 - description: EMC_DLL_XFORM_QUSE10260 - description: EMC_DLL_XFORM_QUSE11261 - description: EMC_DLL_XFORM_QUSE12262 - description: EMC_DLL_XFORM_QUSE13263 - description: EMC_DLL_XFORM_QUSE14264 - description: EMC_DLL_XFORM_QUSE15265 - description: EMC_DLI_TRIM_TXDQS0266 - description: EMC_DLI_TRIM_TXDQS1267 - description: EMC_DLI_TRIM_TXDQS2268 - description: EMC_DLI_TRIM_TXDQS3269 - description: EMC_DLI_TRIM_TXDQS4270 - description: EMC_DLI_TRIM_TXDQS5271 - description: EMC_DLI_TRIM_TXDQS6272 - description: EMC_DLI_TRIM_TXDQS7273 - description: EMC_DLI_TRIM_TXDQS8274 - description: EMC_DLI_TRIM_TXDQS9275 - description: EMC_DLI_TRIM_TXDQS10276 - description: EMC_DLI_TRIM_TXDQS11277 - description: EMC_DLI_TRIM_TXDQS12278 - description: EMC_DLI_TRIM_TXDQS13279 - description: EMC_DLI_TRIM_TXDQS14280 - description: EMC_DLI_TRIM_TXDQS15281 - description: EMC_DLL_XFORM_DQ0282 - description: EMC_DLL_XFORM_DQ1283 - description: EMC_DLL_XFORM_DQ2284 - description: EMC_DLL_XFORM_DQ3285 - description: EMC_DLL_XFORM_DQ4286 - description: EMC_DLL_XFORM_DQ5287 - description: EMC_DLL_XFORM_DQ6288 - description: EMC_DLL_XFORM_DQ7289 - description: EMC_XM2CMDPADCTRL290 - description: EMC_XM2CMDPADCTRL4291 - description: EMC_XM2CMDPADCTRL5292 - description: EMC_XM2DQPADCTRL2293 - description: EMC_XM2DQPADCTRL3294 - description: EMC_XM2CLKPADCTRL295 - description: EMC_XM2CLKPADCTRL2296 - description: EMC_XM2COMPPADCTRL297 - description: EMC_XM2VTTGENPADCTRL298 - description: EMC_XM2VTTGENPADCTRL2299 - description: EMC_XM2VTTGENPADCTRL3300 - description: EMC_XM2DQSPADCTRL3301 - description: EMC_XM2DQSPADCTRL4302 - description: EMC_XM2DQSPADCTRL5303 - description: EMC_XM2DQSPADCTRL6304 - description: EMC_DSR_VTTGEN_DRV305 - description: EMC_TXDSRVTTGEN306 - description: EMC_FBIO_SPARE307 - description: EMC_ZCAL_WAIT_CNT308 - description: EMC_MRS_WAIT_CNT2309 - description: EMC_CTT310 - description: EMC_CTT_DURATION311 - description: EMC_CFG_PIPE312 - description: EMC_DYN_SELF_REF_CONTROL313 - description: EMC_QPOP314 315 required:316 - clock-frequency317 - nvidia,emc-auto-cal-config318 - nvidia,emc-auto-cal-config2319 - nvidia,emc-auto-cal-config3320 - nvidia,emc-auto-cal-interval321 - nvidia,emc-bgbias-ctl0322 - nvidia,emc-cfg323 - nvidia,emc-cfg-2324 - nvidia,emc-ctt-term-ctrl325 - nvidia,emc-mode-1326 - nvidia,emc-mode-2327 - nvidia,emc-mode-4328 - nvidia,emc-mode-reset329 - nvidia,emc-mrs-wait-cnt330 - nvidia,emc-sel-dpd-ctrl331 - nvidia,emc-xm2dqspadctrl2332 - nvidia,emc-zcal-cnt-long333 - nvidia,emc-zcal-interval334 - nvidia,emc-configuration335 336 additionalProperties: false337 338required:339 - compatible340 - reg341 - clocks342 - clock-names343 - nvidia,memory-controller344 - "#interconnect-cells"345 - operating-points-v2346 347additionalProperties: false348 349examples:350 - |351 #include <dt-bindings/clock/tegra124-car.h>352 #include <dt-bindings/interrupt-controller/arm-gic.h>353 354 mc: memory-controller@70019000 {355 compatible = "nvidia,tegra124-mc";356 reg = <0x70019000 0x1000>;357 clocks = <&tegra_car TEGRA124_CLK_MC>;358 clock-names = "mc";359 360 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;361 362 #iommu-cells = <1>;363 #reset-cells = <1>;364 #interconnect-cells = <1>;365 };366 367 external-memory-controller@7001b000 {368 compatible = "nvidia,tegra124-emc";369 reg = <0x7001b000 0x1000>;370 clocks = <&car TEGRA124_CLK_EMC>;371 clock-names = "emc";372 373 nvidia,memory-controller = <&mc>;374 operating-points-v2 = <&dvfs_opp_table>;375 power-domains = <&domain>;376 377 #interconnect-cells = <0>;378 379 emc-timings-0 {380 nvidia,ram-code = <3>;381 382 timing-0 {383 clock-frequency = <12750000>;384 385 nvidia,emc-auto-cal-config = <0xa1430000>;386 nvidia,emc-auto-cal-config2 = <0x00000000>;387 nvidia,emc-auto-cal-config3 = <0x00000000>;388 nvidia,emc-auto-cal-interval = <0x001fffff>;389 nvidia,emc-bgbias-ctl0 = <0x00000008>;390 nvidia,emc-cfg = <0x73240000>;391 nvidia,emc-cfg-2 = <0x000008c5>;392 nvidia,emc-ctt-term-ctrl = <0x00000802>;393 nvidia,emc-mode-1 = <0x80100003>;394 nvidia,emc-mode-2 = <0x80200008>;395 nvidia,emc-mode-4 = <0x00000000>;396 nvidia,emc-mode-reset = <0x80001221>;397 nvidia,emc-mrs-wait-cnt = <0x000e000e>;398 nvidia,emc-sel-dpd-ctrl = <0x00040128>;399 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;400 nvidia,emc-zcal-cnt-long = <0x00000042>;401 nvidia,emc-zcal-interval = <0x00000000>;402 403 nvidia,emc-configuration = <404 0x00000000 /* EMC_RC */405 0x00000003 /* EMC_RFC */406 0x00000000 /* EMC_RFC_SLR */407 0x00000000 /* EMC_RAS */408 0x00000000 /* EMC_RP */409 0x00000004 /* EMC_R2W */410 0x0000000a /* EMC_W2R */411 0x00000003 /* EMC_R2P */412 0x0000000b /* EMC_W2P */413 0x00000000 /* EMC_RD_RCD */414 0x00000000 /* EMC_WR_RCD */415 0x00000003 /* EMC_RRD */416 0x00000003 /* EMC_REXT */417 0x00000000 /* EMC_WEXT */418 0x00000006 /* EMC_WDV */419 0x00000006 /* EMC_WDV_MASK */420 0x00000006 /* EMC_QUSE */421 0x00000002 /* EMC_QUSE_WIDTH */422 0x00000000 /* EMC_IBDLY */423 0x00000005 /* EMC_EINPUT */424 0x00000005 /* EMC_EINPUT_DURATION */425 0x00010000 /* EMC_PUTERM_EXTRA */426 0x00000003 /* EMC_PUTERM_WIDTH */427 0x00000000 /* EMC_PUTERM_ADJ */428 0x00000000 /* EMC_CDB_CNTL_1 */429 0x00000000 /* EMC_CDB_CNTL_2 */430 0x00000000 /* EMC_CDB_CNTL_3 */431 0x00000004 /* EMC_QRST */432 0x0000000c /* EMC_QSAFE */433 0x0000000d /* EMC_RDV */434 0x0000000f /* EMC_RDV_MASK */435 0x00000060 /* EMC_REFRESH */436 0x00000000 /* EMC_BURST_REFRESH_NUM */437 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */438 0x00000002 /* EMC_PDEX2WR */439 0x00000002 /* EMC_PDEX2RD */440 0x00000001 /* EMC_PCHG2PDEN */441 0x00000000 /* EMC_ACT2PDEN */442 0x00000007 /* EMC_AR2PDEN */443 0x0000000f /* EMC_RW2PDEN */444 0x00000005 /* EMC_TXSR */445 0x00000005 /* EMC_TXSRDLL */446 0x00000004 /* EMC_TCKE */447 0x00000005 /* EMC_TCKESR */448 0x00000004 /* EMC_TPD */449 0x00000000 /* EMC_TFAW */450 0x00000000 /* EMC_TRPAB */451 0x00000005 /* EMC_TCLKSTABLE */452 0x00000005 /* EMC_TCLKSTOP */453 0x00000064 /* EMC_TREFBW */454 0x00000000 /* EMC_FBIO_CFG6 */455 0x00000000 /* EMC_ODT_WRITE */456 0x00000000 /* EMC_ODT_READ */457 0x106aa298 /* EMC_FBIO_CFG5 */458 0x002c00a0 /* EMC_CFG_DIG_DLL */459 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */460 0x00064000 /* EMC_DLL_XFORM_DQS0 */461 0x00064000 /* EMC_DLL_XFORM_DQS1 */462 0x00064000 /* EMC_DLL_XFORM_DQS2 */463 0x00064000 /* EMC_DLL_XFORM_DQS3 */464 0x00064000 /* EMC_DLL_XFORM_DQS4 */465 0x00064000 /* EMC_DLL_XFORM_DQS5 */466 0x00064000 /* EMC_DLL_XFORM_DQS6 */467 0x00064000 /* EMC_DLL_XFORM_DQS7 */468 0x00064000 /* EMC_DLL_XFORM_DQS8 */469 0x00064000 /* EMC_DLL_XFORM_DQS9 */470 0x00064000 /* EMC_DLL_XFORM_DQS10 */471 0x00064000 /* EMC_DLL_XFORM_DQS11 */472 0x00064000 /* EMC_DLL_XFORM_DQS12 */473 0x00064000 /* EMC_DLL_XFORM_DQS13 */474 0x00064000 /* EMC_DLL_XFORM_DQS14 */475 0x00064000 /* EMC_DLL_XFORM_DQS15 */476 0x00000000 /* EMC_DLL_XFORM_QUSE0 */477 0x00000000 /* EMC_DLL_XFORM_QUSE1 */478 0x00000000 /* EMC_DLL_XFORM_QUSE2 */479 0x00000000 /* EMC_DLL_XFORM_QUSE3 */480 0x00000000 /* EMC_DLL_XFORM_QUSE4 */481 0x00000000 /* EMC_DLL_XFORM_QUSE5 */482 0x00000000 /* EMC_DLL_XFORM_QUSE6 */483 0x00000000 /* EMC_DLL_XFORM_QUSE7 */484 0x00000000 /* EMC_DLL_XFORM_ADDR0 */485 0x00000000 /* EMC_DLL_XFORM_ADDR1 */486 0x00000000 /* EMC_DLL_XFORM_ADDR2 */487 0x00000000 /* EMC_DLL_XFORM_ADDR3 */488 0x00000000 /* EMC_DLL_XFORM_ADDR4 */489 0x00000000 /* EMC_DLL_XFORM_ADDR5 */490 0x00000000 /* EMC_DLL_XFORM_QUSE8 */491 0x00000000 /* EMC_DLL_XFORM_QUSE9 */492 0x00000000 /* EMC_DLL_XFORM_QUSE10 */493 0x00000000 /* EMC_DLL_XFORM_QUSE11 */494 0x00000000 /* EMC_DLL_XFORM_QUSE12 */495 0x00000000 /* EMC_DLL_XFORM_QUSE13 */496 0x00000000 /* EMC_DLL_XFORM_QUSE14 */497 0x00000000 /* EMC_DLL_XFORM_QUSE15 */498 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */499 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */500 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */501 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */502 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */503 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */504 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */505 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */506 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */507 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */508 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */509 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */510 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */511 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */512 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */513 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */514 0x000fc000 /* EMC_DLL_XFORM_DQ0 */515 0x000fc000 /* EMC_DLL_XFORM_DQ1 */516 0x000fc000 /* EMC_DLL_XFORM_DQ2 */517 0x000fc000 /* EMC_DLL_XFORM_DQ3 */518 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */519 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */520 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */521 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */522 0x10000280 /* EMC_XM2CMDPADCTRL */523 0x00000000 /* EMC_XM2CMDPADCTRL4 */524 0x00111111 /* EMC_XM2CMDPADCTRL5 */525 0x00000000 /* EMC_XM2DQPADCTRL2 */526 0x00000000 /* EMC_XM2DQPADCTRL3 */527 0x77ffc081 /* EMC_XM2CLKPADCTRL */528 0x00000e0e /* EMC_XM2CLKPADCTRL2 */529 0x81f1f108 /* EMC_XM2COMPPADCTRL */530 0x07070004 /* EMC_XM2VTTGENPADCTRL */531 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */532 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */533 0x51451400 /* EMC_XM2DQSPADCTRL3 */534 0x00514514 /* EMC_XM2DQSPADCTRL4 */535 0x00514514 /* EMC_XM2DQSPADCTRL5 */536 0x51451400 /* EMC_XM2DQSPADCTRL6 */537 0x0000003f /* EMC_DSR_VTTGEN_DRV */538 0x00000007 /* EMC_TXDSRVTTGEN */539 0x00000000 /* EMC_FBIO_SPARE */540 0x00000042 /* EMC_ZCAL_WAIT_CNT */541 0x000e000e /* EMC_MRS_WAIT_CNT2 */542 0x00000000 /* EMC_CTT */543 0x00000003 /* EMC_CTT_DURATION */544 0x0000f2f3 /* EMC_CFG_PIPE */545 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */546 0x0000000a /* EMC_QPOP */547 >;548 };549 };550 };551