277 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra186 (and later) SoC Memory Controller8 9maintainers:10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>12 13description: |14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC16 handles memory requests for 40-bit virtual addresses from internal clients17 and arbitrates among them to allocate memory bandwidth.18 19 Up to 15 GiB of physical memory can be supported. Security features such as20 encryption of traffic to and from DRAM via general security apertures are21 available for video and other secure applications, as well as DRAM ECC for22 automotive safety applications (single bit error correction and double bit23 error detection).24 25properties:26 $nodename:27 pattern: "^memory-controller@[0-9a-f]+$"28 29 compatible:30 items:31 - enum:32 - nvidia,tegra186-mc33 - nvidia,tegra194-mc34 - nvidia,tegra234-mc35 36 reg:37 minItems: 638 maxItems: 1839 40 reg-names:41 minItems: 642 maxItems: 1843 44 interrupts:45 items:46 - description: MC general interrupt47 48 "#address-cells":49 const: 250 51 "#size-cells":52 const: 253 54 ranges: true55 56 dma-ranges: true57 58 "#interconnect-cells":59 const: 160 61patternProperties:62 "^external-memory-controller@[0-9a-f]+$":63 description:64 The bulk of the work involved in controlling the external memory65 controller on NVIDIA Tegra186 and later is performed on the BPMP. This66 coprocessor exposes the EMC clock that is used to set the frequency at67 which the external memory is clocked and a remote procedure call that68 can be used to obtain the set of available frequencies.69 type: object70 properties:71 compatible:72 items:73 - enum:74 - nvidia,tegra186-emc75 - nvidia,tegra194-emc76 - nvidia,tegra234-emc77 78 reg:79 minItems: 180 maxItems: 281 82 interrupts:83 items:84 - description: EMC general interrupt85 86 clocks:87 items:88 - description: external memory clock89 90 clock-names:91 items:92 - const: emc93 94 "#interconnect-cells":95 const: 096 97 nvidia,bpmp:98 $ref: /schemas/types.yaml#/definitions/phandle99 description:100 phandle of the node representing the BPMP101 102 allOf:103 - if:104 properties:105 compatible:106 const: nvidia,tegra186-emc107 then:108 properties:109 reg:110 maxItems: 1111 112 - if:113 properties:114 compatible:115 const: nvidia,tegra194-emc116 then:117 properties:118 reg:119 minItems: 2120 121 - if:122 properties:123 compatible:124 const: nvidia,tegra234-emc125 then:126 properties:127 reg:128 minItems: 2129 130 additionalProperties: false131 132 required:133 - compatible134 - reg135 - interrupts136 - clocks137 - clock-names138 - "#interconnect-cells"139 - nvidia,bpmp140 141allOf:142 - if:143 properties:144 compatible:145 const: nvidia,tegra186-mc146 then:147 properties:148 reg:149 maxItems: 6150 description: 5 memory controller channels and 1 for stream-id registers151 152 reg-names:153 items:154 - const: sid155 - const: broadcast156 - const: ch0157 - const: ch1158 - const: ch2159 - const: ch3160 161 - if:162 properties:163 compatible:164 const: nvidia,tegra194-mc165 then:166 properties:167 reg:168 minItems: 18169 description: 17 memory controller channels and 1 for stream-id registers170 171 reg-names:172 items:173 - const: sid174 - const: broadcast175 - const: ch0176 - const: ch1177 - const: ch2178 - const: ch3179 - const: ch4180 - const: ch5181 - const: ch6182 - const: ch7183 - const: ch8184 - const: ch9185 - const: ch10186 - const: ch11187 - const: ch12188 - const: ch13189 - const: ch14190 - const: ch15191 192 - if:193 properties:194 compatible:195 const: nvidia,tegra234-mc196 then:197 properties:198 reg:199 minItems: 18200 description: 17 memory controller channels and 1 for stream-id registers201 202 reg-names:203 items:204 - const: sid205 - const: broadcast206 - const: ch0207 - const: ch1208 - const: ch2209 - const: ch3210 - const: ch4211 - const: ch5212 - const: ch6213 - const: ch7214 - const: ch8215 - const: ch9216 - const: ch10217 - const: ch11218 - const: ch12219 - const: ch13220 - const: ch14221 - const: ch15222 223additionalProperties: false224 225required:226 - compatible227 - reg228 - reg-names229 - interrupts230 - "#address-cells"231 - "#size-cells"232 233examples:234 - |235 #include <dt-bindings/clock/tegra186-clock.h>236 #include <dt-bindings/interrupt-controller/arm-gic.h>237 238 bus {239 #address-cells = <2>;240 #size-cells = <2>;241 242 memory-controller@2c00000 {243 compatible = "nvidia,tegra186-mc";244 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */245 <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */246 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */247 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */248 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */249 <0x0 0x02c50000 0x0 0x10000>; /* MC3 */250 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";251 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;252 253 #address-cells = <2>;254 #size-cells = <2>;255 256 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;257 258 /*259 * Memory clients have access to all 40 bits that the memory260 * controller can address.261 */262 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;263 264 external-memory-controller@2c60000 {265 compatible = "nvidia,tegra186-emc";266 reg = <0x0 0x02c60000 0x0 0x50000>;267 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;268 clocks = <&bpmp TEGRA186_CLK_EMC>;269 clock-names = "emc";270 271 #interconnect-cells = <0>;272 273 nvidia,bpmp = <&bpmp>;274 };275 };276 };277