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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra20 SoC External Memory Controller8 9maintainers:10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>13 14description: |15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to16 service the request stream sent from Memory Controller. The EMC also has17 various performance-affecting settings beyond the obvious SDRAM configuration18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC19 standard protocols: DDR1, LPDDR2 and DDR2.20 21properties:22 compatible:23 const: nvidia,tegra20-emc24 25 reg:26 maxItems: 127 28 clocks:29 maxItems: 130 31 interrupts:32 maxItems: 133 34 "#address-cells":35 const: 136 37 "#size-cells":38 const: 039 40 "#interconnect-cells":41 const: 042 43 nvidia,memory-controller:44 $ref: /schemas/types.yaml#/definitions/phandle45 description:46 Phandle of the Memory Controller node.47 48 power-domains:49 maxItems: 150 description:51 Phandle of the SoC "core" power domain.52 53 operating-points-v2:54 description:55 Should contain freqs and voltages and opp-supported-hw property, which56 is a bitfield indicating SoC process ID mask.57 58 nvidia,use-ram-code:59 type: boolean60 description:61 If present, the emc-tables@ sub-nodes will be addressed.62 63$defs:64 emc-table:65 type: object66 properties:67 compatible:68 const: nvidia,tegra20-emc-table69 70 clock-frequency:71 description:72 Memory clock rate in kHz.73 minimum: 100074 maximum: 90000075 76 reg:77 maxItems: 178 description:79 Either an opaque enumerator to tell different tables apart, or80 the valid frequency for which the table should be used (in kHz).81 82 nvidia,emc-registers:83 description:84 EMC timing characterization data. These are the registers85 (see section "15.4.1 EMC Registers" in the TRM) whose values86 need to be specified, according to the board documentation.87 $ref: /schemas/types.yaml#/definitions/uint32-array88 items:89 - description: EMC_RC90 - description: EMC_RFC91 - description: EMC_RAS92 - description: EMC_RP93 - description: EMC_R2W94 - description: EMC_W2R95 - description: EMC_R2P96 - description: EMC_W2P97 - description: EMC_RD_RCD98 - description: EMC_WR_RCD99 - description: EMC_RRD100 - description: EMC_REXT101 - description: EMC_WDV102 - description: EMC_QUSE103 - description: EMC_QRST104 - description: EMC_QSAFE105 - description: EMC_RDV106 - description: EMC_REFRESH107 - description: EMC_BURST_REFRESH_NUM108 - description: EMC_PDEX2WR109 - description: EMC_PDEX2RD110 - description: EMC_PCHG2PDEN111 - description: EMC_ACT2PDEN112 - description: EMC_AR2PDEN113 - description: EMC_RW2PDEN114 - description: EMC_TXSR115 - description: EMC_TCKE116 - description: EMC_TFAW117 - description: EMC_TRPAB118 - description: EMC_TCLKSTABLE119 - description: EMC_TCLKSTOP120 - description: EMC_TREFBW121 - description: EMC_QUSE_EXTRA122 - description: EMC_FBIO_CFG6123 - description: EMC_ODT_WRITE124 - description: EMC_ODT_READ125 - description: EMC_FBIO_CFG5126 - description: EMC_CFG_DIG_DLL127 - description: EMC_DLL_XFORM_DQS128 - description: EMC_DLL_XFORM_QUSE129 - description: EMC_ZCAL_REF_CNT130 - description: EMC_ZCAL_WAIT_CNT131 - description: EMC_AUTO_CAL_INTERVAL132 - description: EMC_CFG_CLKTRIM_0133 - description: EMC_CFG_CLKTRIM_1134 - description: EMC_CFG_CLKTRIM_2135 136 required:137 - clock-frequency138 - compatible139 - reg140 - nvidia,emc-registers141 142 additionalProperties: false143 144patternProperties:145 "^emc-table@[0-9]+$":146 $ref: "#/$defs/emc-table"147 148 "^emc-tables@[a-f0-9-]+$":149 type: object150 properties:151 reg:152 maxItems: 1153 description:154 An opaque enumerator to tell different tables apart.155 156 nvidia,ram-code:157 $ref: /schemas/types.yaml#/definitions/uint32158 description:159 Value of RAM_CODE this timing set is used for.160 161 "#address-cells":162 const: 1163 164 "#size-cells":165 const: 0166 167 lpddr2:168 $ref: ddr/jedec,lpddr2.yaml#169 type: object170 171 patternProperties:172 "^emc-table@[0-9]+$":173 $ref: "#/$defs/emc-table"174 175 oneOf:176 - required:177 - nvidia,ram-code178 179 - required:180 - lpddr2181 182 additionalProperties: false183 184required:185 - compatible186 - reg187 - interrupts188 - clocks189 - nvidia,memory-controller190 - "#interconnect-cells"191 - operating-points-v2192 193additionalProperties: false194 195examples:196 - |197 external-memory-controller@7000f400 {198 compatible = "nvidia,tegra20-emc";199 reg = <0x7000f400 0x400>;200 interrupts = <0 78 4>;201 clocks = <&clock_controller 57>;202 203 nvidia,memory-controller = <&mc>;204 operating-points-v2 = <&dvfs_opp_table>;205 power-domains = <&domain>;206 207 #interconnect-cells = <0>;208 #address-cells = <1>;209 #size-cells = <0>;210 211 nvidia,use-ram-code;212 213 emc-tables@0 {214 nvidia,ram-code = <0>;215 reg = <0>;216 217 #address-cells = <1>;218 #size-cells = <0>;219 220 emc-table@333000 {221 reg = <333000>;222 compatible = "nvidia,tegra20-emc-table";223 clock-frequency = <333000>;224 nvidia,emc-registers = <0x00000018 0x00000033225 0x00000012 0x00000004 0x00000004 0x00000005226 0x00000003 0x0000000c 0x00000006 0x00000006227 0x00000003 0x00000001 0x00000004 0x00000005228 0x00000004 0x00000009 0x0000000d 0x00000bff229 0x00000000 0x00000003 0x00000003 0x00000006230 0x00000006 0x00000001 0x00000011 0x000000c8231 0x00000003 0x0000000e 0x00000007 0x00000008232 0x00000002 0x00000000 0x00000000 0x00000002233 0x00000000 0x00000000 0x00000083 0xf0440303234 0x007fe010 0x00001414 0x00000000 0x00000000235 0x00000000 0x00000000 0x00000000 0x00000000>;236 };237 };238 239 emc-tables@1 {240 reg = <1>;241 242 lpddr2 {243 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";244 revision-id1 = <1>;245 density = <2048>;246 io-width = <16>;247 };248 };249 };250