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1# SPDX-License-Identifier: (GPL-2.0)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra30 SoC External Memory Controller8 9maintainers:10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>13 14description: |15 The EMC interfaces with the off-chip SDRAM to service the request stream16 sent from Memory Controller. The EMC also has various performance-affecting17 settings beyond the obvious SDRAM configuration parameters and initialization18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,19 LPDDR3, and DDR3.20 21properties:22 compatible:23 const: nvidia,tegra30-emc24 25 reg:26 maxItems: 127 28 clocks:29 maxItems: 130 31 interrupts:32 maxItems: 133 34 "#interconnect-cells":35 const: 036 37 nvidia,memory-controller:38 $ref: /schemas/types.yaml#/definitions/phandle39 description:40 Phandle of the Memory Controller node.41 42 power-domains:43 maxItems: 144 description:45 Phandle of the SoC "core" power domain.46 47 operating-points-v2:48 description:49 Should contain freqs and voltages and opp-supported-hw property, which50 is a bitfield indicating SoC speedo ID mask.51 52patternProperties:53 "^emc-timings-[0-9]+$":54 type: object55 properties:56 nvidia,ram-code:57 $ref: /schemas/types.yaml#/definitions/uint3258 description:59 Value of RAM_CODE this timing set is used for.60 61 patternProperties:62 "^timing-[0-9]+$":63 type: object64 properties:65 clock-frequency:66 description:67 Memory clock rate in Hz.68 minimum: 100000069 maximum: 90000000070 71 nvidia,emc-auto-cal-interval:72 description:73 Pad calibration interval in microseconds.74 $ref: /schemas/types.yaml#/definitions/uint3275 minimum: 076 maximum: 209715177 78 nvidia,emc-mode-1:79 $ref: /schemas/types.yaml#/definitions/uint3280 description:81 Mode Register 1.82 83 nvidia,emc-mode-2:84 $ref: /schemas/types.yaml#/definitions/uint3285 description:86 Mode Register 2.87 88 nvidia,emc-mode-reset:89 $ref: /schemas/types.yaml#/definitions/uint3290 description:91 Mode Register 0.92 93 nvidia,emc-zcal-cnt-long:94 description:95 Number of EMC clocks to wait before issuing any commands after96 sending ZCAL_MRW_CMD.97 $ref: /schemas/types.yaml#/definitions/uint3298 minimum: 099 maximum: 1023100 101 nvidia,emc-cfg-dyn-self-ref:102 type: boolean103 description:104 Dynamic self-refresh enabled.105 106 nvidia,emc-cfg-periodic-qrst:107 type: boolean108 description:109 FBIO "read" FIFO periodic resetting enabled.110 111 nvidia,emc-configuration:112 description:113 EMC timing characterization data. These are the registers114 (see section "18.13.2 EMC Registers" in the TRM) whose values115 need to be specified, according to the board documentation.116 $ref: /schemas/types.yaml#/definitions/uint32-array117 items:118 - description: EMC_RC119 - description: EMC_RFC120 - description: EMC_RAS121 - description: EMC_RP122 - description: EMC_R2W123 - description: EMC_W2R124 - description: EMC_R2P125 - description: EMC_W2P126 - description: EMC_RD_RCD127 - description: EMC_WR_RCD128 - description: EMC_RRD129 - description: EMC_REXT130 - description: EMC_WEXT131 - description: EMC_WDV132 - description: EMC_QUSE133 - description: EMC_QRST134 - description: EMC_QSAFE135 - description: EMC_RDV136 - description: EMC_REFRESH137 - description: EMC_BURST_REFRESH_NUM138 - description: EMC_PRE_REFRESH_REQ_CNT139 - description: EMC_PDEX2WR140 - description: EMC_PDEX2RD141 - description: EMC_PCHG2PDEN142 - description: EMC_ACT2PDEN143 - description: EMC_AR2PDEN144 - description: EMC_RW2PDEN145 - description: EMC_TXSR146 - description: EMC_TXSRDLL147 - description: EMC_TCKE148 - description: EMC_TFAW149 - description: EMC_TRPAB150 - description: EMC_TCLKSTABLE151 - description: EMC_TCLKSTOP152 - description: EMC_TREFBW153 - description: EMC_QUSE_EXTRA154 - description: EMC_FBIO_CFG6155 - description: EMC_ODT_WRITE156 - description: EMC_ODT_READ157 - description: EMC_FBIO_CFG5158 - description: EMC_CFG_DIG_DLL159 - description: EMC_CFG_DIG_DLL_PERIOD160 - description: EMC_DLL_XFORM_DQS0161 - description: EMC_DLL_XFORM_DQS1162 - description: EMC_DLL_XFORM_DQS2163 - description: EMC_DLL_XFORM_DQS3164 - description: EMC_DLL_XFORM_DQS4165 - description: EMC_DLL_XFORM_DQS5166 - description: EMC_DLL_XFORM_DQS6167 - description: EMC_DLL_XFORM_DQS7168 - description: EMC_DLL_XFORM_QUSE0169 - description: EMC_DLL_XFORM_QUSE1170 - description: EMC_DLL_XFORM_QUSE2171 - description: EMC_DLL_XFORM_QUSE3172 - description: EMC_DLL_XFORM_QUSE4173 - description: EMC_DLL_XFORM_QUSE5174 - description: EMC_DLL_XFORM_QUSE6175 - description: EMC_DLL_XFORM_QUSE7176 - description: EMC_DLI_TRIM_TXDQS0177 - description: EMC_DLI_TRIM_TXDQS1178 - description: EMC_DLI_TRIM_TXDQS2179 - description: EMC_DLI_TRIM_TXDQS3180 - description: EMC_DLI_TRIM_TXDQS4181 - description: EMC_DLI_TRIM_TXDQS5182 - description: EMC_DLI_TRIM_TXDQS6183 - description: EMC_DLI_TRIM_TXDQS7184 - description: EMC_DLL_XFORM_DQ0185 - description: EMC_DLL_XFORM_DQ1186 - description: EMC_DLL_XFORM_DQ2187 - description: EMC_DLL_XFORM_DQ3188 - description: EMC_XM2CMDPADCTRL189 - description: EMC_XM2DQSPADCTRL2190 - description: EMC_XM2DQPADCTRL2191 - description: EMC_XM2CLKPADCTRL192 - description: EMC_XM2COMPPADCTRL193 - description: EMC_XM2VTTGENPADCTRL194 - description: EMC_XM2VTTGENPADCTRL2195 - description: EMC_XM2QUSEPADCTRL196 - description: EMC_XM2DQSPADCTRL3197 - description: EMC_CTT_TERM_CTRL198 - description: EMC_ZCAL_INTERVAL199 - description: EMC_ZCAL_WAIT_CNT200 - description: EMC_MRS_WAIT_CNT201 - description: EMC_AUTO_CAL_CONFIG202 - description: EMC_CTT203 - description: EMC_CTT_DURATION204 - description: EMC_DYN_SELF_REF_CONTROL205 - description: EMC_FBIO_SPARE206 - description: EMC_CFG_RSV207 208 required:209 - clock-frequency210 - nvidia,emc-auto-cal-interval211 - nvidia,emc-mode-1212 - nvidia,emc-mode-2213 - nvidia,emc-mode-reset214 - nvidia,emc-zcal-cnt-long215 - nvidia,emc-configuration216 217 additionalProperties: false218 219 required:220 - nvidia,ram-code221 222 additionalProperties: false223 224required:225 - compatible226 - reg227 - interrupts228 - clocks229 - nvidia,memory-controller230 - "#interconnect-cells"231 - operating-points-v2232 233additionalProperties: false234 235examples:236 - |237 external-memory-controller@7000f400 {238 compatible = "nvidia,tegra30-emc";239 reg = <0x7000f400 0x400>;240 interrupts = <0 78 4>;241 clocks = <&tegra_car 57>;242 243 nvidia,memory-controller = <&mc>;244 operating-points-v2 = <&dvfs_opp_table>;245 power-domains = <&domain>;246 247 #interconnect-cells = <0>;248 249 emc-timings-1 {250 nvidia,ram-code = <1>;251 252 timing-667000000 {253 clock-frequency = <667000000>;254 255 nvidia,emc-auto-cal-interval = <0x001fffff>;256 nvidia,emc-mode-1 = <0x80100002>;257 nvidia,emc-mode-2 = <0x80200018>;258 nvidia,emc-mode-reset = <0x80000b71>;259 nvidia,emc-zcal-cnt-long = <0x00000040>;260 nvidia,emc-cfg-periodic-qrst;261 262 nvidia,emc-configuration = <263 0x00000020 /* EMC_RC */264 0x0000006a /* EMC_RFC */265 0x00000017 /* EMC_RAS */266 0x00000007 /* EMC_RP */267 0x00000005 /* EMC_R2W */268 0x0000000c /* EMC_W2R */269 0x00000003 /* EMC_R2P */270 0x00000011 /* EMC_W2P */271 0x00000007 /* EMC_RD_RCD */272 0x00000007 /* EMC_WR_RCD */273 0x00000002 /* EMC_RRD */274 0x00000001 /* EMC_REXT */275 0x00000000 /* EMC_WEXT */276 0x00000007 /* EMC_WDV */277 0x0000000a /* EMC_QUSE */278 0x00000009 /* EMC_QRST */279 0x0000000b /* EMC_QSAFE */280 0x00000011 /* EMC_RDV */281 0x00001412 /* EMC_REFRESH */282 0x00000000 /* EMC_BURST_REFRESH_NUM */283 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */284 0x00000002 /* EMC_PDEX2WR */285 0x0000000e /* EMC_PDEX2RD */286 0x00000001 /* EMC_PCHG2PDEN */287 0x00000000 /* EMC_ACT2PDEN */288 0x0000000c /* EMC_AR2PDEN */289 0x00000016 /* EMC_RW2PDEN */290 0x00000072 /* EMC_TXSR */291 0x00000200 /* EMC_TXSRDLL */292 0x00000005 /* EMC_TCKE */293 0x00000015 /* EMC_TFAW */294 0x00000000 /* EMC_TRPAB */295 0x00000006 /* EMC_TCLKSTABLE */296 0x00000007 /* EMC_TCLKSTOP */297 0x00001453 /* EMC_TREFBW */298 0x0000000b /* EMC_QUSE_EXTRA */299 0x00000006 /* EMC_FBIO_CFG6 */300 0x00000000 /* EMC_ODT_WRITE */301 0x00000000 /* EMC_ODT_READ */302 0x00005088 /* EMC_FBIO_CFG5 */303 0xf00b0191 /* EMC_CFG_DIG_DLL */304 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */305 0x00000008 /* EMC_DLL_XFORM_DQS0 */306 0x00000008 /* EMC_DLL_XFORM_DQS1 */307 0x00000008 /* EMC_DLL_XFORM_DQS2 */308 0x00000008 /* EMC_DLL_XFORM_DQS3 */309 0x0000000a /* EMC_DLL_XFORM_DQS4 */310 0x0000000a /* EMC_DLL_XFORM_DQS5 */311 0x0000000a /* EMC_DLL_XFORM_DQS6 */312 0x0000000a /* EMC_DLL_XFORM_DQS7 */313 0x00018000 /* EMC_DLL_XFORM_QUSE0 */314 0x00018000 /* EMC_DLL_XFORM_QUSE1 */315 0x00018000 /* EMC_DLL_XFORM_QUSE2 */316 0x00018000 /* EMC_DLL_XFORM_QUSE3 */317 0x00000000 /* EMC_DLL_XFORM_QUSE4 */318 0x00000000 /* EMC_DLL_XFORM_QUSE5 */319 0x00000000 /* EMC_DLL_XFORM_QUSE6 */320 0x00000000 /* EMC_DLL_XFORM_QUSE7 */321 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */322 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */323 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */324 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */325 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */326 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */327 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */328 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */329 0x0000000a /* EMC_DLL_XFORM_DQ0 */330 0x0000000a /* EMC_DLL_XFORM_DQ1 */331 0x0000000a /* EMC_DLL_XFORM_DQ2 */332 0x0000000a /* EMC_DLL_XFORM_DQ3 */333 0x000002a0 /* EMC_XM2CMDPADCTRL */334 0x0800013d /* EMC_XM2DQSPADCTRL2 */335 0x22220000 /* EMC_XM2DQPADCTRL2 */336 0x77fff884 /* EMC_XM2CLKPADCTRL */337 0x01f1f501 /* EMC_XM2COMPPADCTRL */338 0x07077404 /* EMC_XM2VTTGENPADCTRL */339 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */340 0x080001e8 /* EMC_XM2QUSEPADCTRL */341 0x0c000021 /* EMC_XM2DQSPADCTRL3 */342 0x00000802 /* EMC_CTT_TERM_CTRL */343 0x00020000 /* EMC_ZCAL_INTERVAL */344 0x00000100 /* EMC_ZCAL_WAIT_CNT */345 0x0155000c /* EMC_MRS_WAIT_CNT */346 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */347 0x00000000 /* EMC_CTT */348 0x00000000 /* EMC_CTT_DURATION */349 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */350 0xe8000000 /* EMC_FBIO_SPARE */351 0xff00ff49 /* EMC_CFG_RSV */352 >;353 };354 };355 };356