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1# SPDX-License-Identifier: (GPL-2.0)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra30 SoC Memory Controller8 9maintainers:10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>13 14description: |15 Tegra30 Memory Controller architecturally consists of the following parts:16 17 Arbitration Domains, which can handle a single request or response per18 clock from a group of clients. Typically, a system has a single Arbitration19 Domain, but an implementation may divide the client space into multiple20 Arbitration Domains to increase the effective system bandwidth.21 22 Protocol Arbiter, which manage a related pool of memory devices. A system23 may have a single Protocol Arbiter or multiple Protocol Arbiters.24 25 Memory Crossbar, which routes request and responses between Arbitration26 Domains and Protocol Arbiters. In the simplest version of the system, the27 Memory Crossbar is just a pass through between a single Arbitration Domain28 and a single Protocol Arbiter.29 30 Global Resources, which include things like configuration registers which31 are shared across the Memory Subsystem.32 33 The Tegra30 Memory Controller handles memory requests from internal clients34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR235 SDRAMs.36 37properties:38 compatible:39 const: nvidia,tegra30-mc40 41 reg:42 maxItems: 143 44 clocks:45 maxItems: 146 47 clock-names:48 items:49 - const: mc50 51 interrupts:52 maxItems: 153 54 "#reset-cells":55 const: 156 57 "#iommu-cells":58 const: 159 60 "#interconnect-cells":61 const: 162 63patternProperties:64 "^emc-timings-[0-9]+$":65 type: object66 properties:67 nvidia,ram-code:68 $ref: /schemas/types.yaml#/definitions/uint3269 description:70 Value of RAM_CODE this timing set is used for.71 72 patternProperties:73 "^timing-[0-9]+$":74 type: object75 properties:76 clock-frequency:77 description:78 Memory clock rate in Hz.79 minimum: 100000080 maximum: 90000000081 82 nvidia,emem-configuration:83 $ref: /schemas/types.yaml#/definitions/uint32-array84 description: |85 Values to be written to the EMEM register block. See section86 "18.13.1 MC Registers" in the TRM.87 items:88 - description: MC_EMEM_ARB_CFG89 - description: MC_EMEM_ARB_OUTSTANDING_REQ90 - description: MC_EMEM_ARB_TIMING_RCD91 - description: MC_EMEM_ARB_TIMING_RP92 - description: MC_EMEM_ARB_TIMING_RC93 - description: MC_EMEM_ARB_TIMING_RAS94 - description: MC_EMEM_ARB_TIMING_FAW95 - description: MC_EMEM_ARB_TIMING_RRD96 - description: MC_EMEM_ARB_TIMING_RAP2PRE97 - description: MC_EMEM_ARB_TIMING_WAP2PRE98 - description: MC_EMEM_ARB_TIMING_R2R99 - description: MC_EMEM_ARB_TIMING_W2W100 - description: MC_EMEM_ARB_TIMING_R2W101 - description: MC_EMEM_ARB_TIMING_W2R102 - description: MC_EMEM_ARB_DA_TURNS103 - description: MC_EMEM_ARB_DA_COVERS104 - description: MC_EMEM_ARB_MISC0105 - description: MC_EMEM_ARB_RING1_THROTTLE106 107 required:108 - clock-frequency109 - nvidia,emem-configuration110 111 additionalProperties: false112 113 required:114 - nvidia,ram-code115 116 additionalProperties: false117 118required:119 - compatible120 - reg121 - interrupts122 - clocks123 - clock-names124 - "#reset-cells"125 - "#iommu-cells"126 - "#interconnect-cells"127 128additionalProperties: false129 130examples:131 - |132 memory-controller@7000f000 {133 compatible = "nvidia,tegra30-mc";134 reg = <0x7000f000 0x400>;135 clocks = <&tegra_car 32>;136 clock-names = "mc";137 138 interrupts = <0 77 4>;139 140 #iommu-cells = <1>;141 #reset-cells = <1>;142 #interconnect-cells = <1>;143 144 emc-timings-1 {145 nvidia,ram-code = <1>;146 147 timing-667000000 {148 clock-frequency = <667000000>;149 150 nvidia,emem-configuration = <151 0x0000000a /* MC_EMEM_ARB_CFG */152 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */153 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */154 0x00000004 /* MC_EMEM_ARB_TIMING_RP */155 0x00000010 /* MC_EMEM_ARB_TIMING_RC */156 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */157 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */158 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */159 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */160 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */161 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */162 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */163 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */164 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */165 0x08040202 /* MC_EMEM_ARB_DA_TURNS */166 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */167 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */168 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */169 >;170 };171 };172 };173