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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller8 9maintainers:10 - Krzysztof Kozlowski <krzk@kernel.org>11 12description: |13 The DDR controller of the AR7xxx and AR9xxx families provides an interface to14 flush the FIFO between various devices and the DDR. This is mainly used by15 the IRQ controller to flush the FIFO before running the interrupt handler of16 such devices.17 18properties:19 compatible:20 oneOf:21 - items:22 - const: qca,ar9132-ddr-controller23 - const: qca,ar7240-ddr-controller24 - items:25 - enum:26 - qca,ar7100-ddr-controller27 - qca,ar7240-ddr-controller28 29 "#qca,ddr-wb-channel-cells":30 description: |31 Specifies the number of cells needed to encode the write buffer channel32 index.33 $ref: /schemas/types.yaml#/definitions/uint3234 const: 135 36 reg:37 maxItems: 138 39required:40 - compatible41 - "#qca,ddr-wb-channel-cells"42 - reg43 44additionalProperties: false45 46examples:47 - |48 ddr_ctrl: memory-controller@18000000 {49 compatible = "qca,ar9132-ddr-controller",50 "qca,ar7240-ddr-controller";51 reg = <0x18000000 0x100>;52 53 #qca,ddr-wb-channel-cells = <1>;54 };55 56 interrupt-controller {57 // ...58 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;59 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,60 <&ddr_ctrl 0>, <&ddr_ctrl 1>;61 };62