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1# SPDX-License-Identifier: GPL-2.0-only2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys DesignWare Universal Multi-Protocol Memory Controller8 9maintainers:10 - Krzysztof Kozlowski <krzk@kernel.org>11 - Michal Simek <michal.simek@amd.com>12 13description: |14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of15 working with the memory devices supporting up to (LP)DDR4 protocol. It can16 be equipped with SEC/DEC ECC feature if DRAM data bus width is either17 16-bits or 32-bits or 64-bits wide.18 19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a20 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits21 bus width configurations.22 23properties:24 compatible:25 oneOf:26 - deprecated: true27 description: Synopsys DW uMCTL2 DDR controller v3.80a28 const: snps,ddrc-3.80a29 - description: Synopsys DW uMCTL2 DDR controller30 const: snps,dw-umctl2-ddrc31 - description: Xilinx ZynqMP DDR controller v2.40a32 const: xlnx,zynqmp-ddrc-2.40a33 34 interrupts:35 description:36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"37 ECC Corrected Error, ECC Uncorrected Error, ECC Address Protection,38 Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the39 signals merged before they reach the IRQ controller or have some of them40 absent in case if the corresponding feature is unavailable/disabled.41 minItems: 142 maxItems: 543 44 interrupt-names:45 minItems: 146 maxItems: 547 oneOf:48 - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ49 items:50 - const: ecc51 - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs52 items:53 enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ]54 55 reg:56 maxItems: 157 58 clocks:59 description:60 A standard set of the clock sources contains CSRs bus clock, AXI-ports61 reference clock, DDRC core clock, Scrubber standalone clock62 (synchronous to the DDRC clock).63 minItems: 164 maxItems: 465 66 clock-names:67 minItems: 168 maxItems: 469 items:70 enum: [ pclk, aclk, core, sbr ]71 72 resets:73 description:74 Each clock domain can have separate reset signal.75 minItems: 176 maxItems: 477 78 reset-names:79 minItems: 180 maxItems: 481 items:82 enum: [ prst, arst, core, sbr ]83 84required:85 - compatible86 - reg87 - interrupts88 89additionalProperties: false90 91examples:92 - |93 #include <dt-bindings/interrupt-controller/arm-gic.h>94 95 memory-controller@fd070000 {96 compatible = "xlnx,zynqmp-ddrc-2.40a";97 reg = <0xfd070000 0x30000>;98 99 interrupt-parent = <&gic>;100 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;101 interrupt-names = "ecc";102 };103 - |104 #include <dt-bindings/interrupt-controller/irq.h>105 106 memory-controller@3d400000 {107 compatible = "snps,dw-umctl2-ddrc";108 reg = <0x3d400000 0x400000>;109 110 interrupts = <147 IRQ_TYPE_LEVEL_HIGH>, <148 IRQ_TYPE_LEVEL_HIGH>,111 <149 IRQ_TYPE_LEVEL_HIGH>, <150 IRQ_TYPE_LEVEL_HIGH>;112 interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";113 114 clocks = <&pclk>, <&aclk>, <&core_clk>, <&sbr_clk>;115 clock-names = "pclk", "aclk", "core", "sbr";116 };117...118