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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Peripheral properties for ST FMC2 Controller8 9maintainers:10 - Christophe Kerello <christophe.kerello@foss.st.com>11 - Marek Vasut <marex@denx.de>12 13properties:14 st,fmc2-ebi-cs-transaction-type:15 description: |16 Select one of the transactions type supported17 0: Asynchronous mode 1 SRAM/FRAM.18 1: Asynchronous mode 1 PSRAM.19 2: Asynchronous mode A SRAM/FRAM.20 3: Asynchronous mode A PSRAM.21 4: Asynchronous mode 2 NOR.22 5: Asynchronous mode B NOR.23 6: Asynchronous mode C NOR.24 7: Asynchronous mode D NOR.25 8: Synchronous read synchronous write PSRAM.26 9: Synchronous read asynchronous write PSRAM.27 10: Synchronous read synchronous write NOR.28 11: Synchronous read asynchronous write NOR.29 $ref: /schemas/types.yaml#/definitions/uint3230 minimum: 031 maximum: 1132 33 st,fmc2-ebi-cs-cclk-enable:34 description: Continuous clock enable (first bank must be configured35 in synchronous mode). The FMC_CLK is generated continuously36 during asynchronous and synchronous access. By default, the37 FMC_CLK is only generated during synchronous access.38 $ref: /schemas/types.yaml#/definitions/flag39 40 st,fmc2-ebi-cs-mux-enable:41 description: Address/Data multiplexed on databus (valid only with42 NOR and PSRAM transactions type). By default, Address/Data43 are not multiplexed.44 $ref: /schemas/types.yaml#/definitions/flag45 46 st,fmc2-ebi-cs-buswidth:47 description: Data bus width48 $ref: /schemas/types.yaml#/definitions/uint3249 enum: [ 8, 16 ]50 default: 1651 52 st,fmc2-ebi-cs-waitpol-high:53 description: Wait signal polarity (NWAIT signal active high).54 By default, NWAIT is active low.55 $ref: /schemas/types.yaml#/definitions/flag56 57 st,fmc2-ebi-cs-waitcfg-enable:58 description: The NWAIT signal indicates wheither the data from the59 device are valid or if a wait state must be inserted when accessing60 the device in synchronous mode. By default, the NWAIT signal is61 active one data cycle before wait state.62 $ref: /schemas/types.yaml#/definitions/flag63 64 st,fmc2-ebi-cs-wait-enable:65 description: The NWAIT signal is enabled (its level is taken into66 account after the programmed latency period to insert wait states67 if asserted). By default, the NWAIT signal is disabled.68 $ref: /schemas/types.yaml#/definitions/flag69 70 st,fmc2-ebi-cs-asyncwait-enable:71 description: The NWAIT signal is taken into account during asynchronous72 transactions. By default, the NWAIT signal is not taken into account73 during asynchronous transactions.74 $ref: /schemas/types.yaml#/definitions/flag75 76 st,fmc2-ebi-cs-cpsize:77 description: CRAM page size. The controller splits the burst access78 when the memory page is reached. By default, no burst split when79 crossing page boundary.80 $ref: /schemas/types.yaml#/definitions/uint3281 enum: [ 0, 128, 256, 512, 1024 ]82 default: 083 84 st,fmc2-ebi-cs-byte-lane-setup-ns:85 description: This property configures the byte lane setup timing86 defined in nanoseconds from NBLx low to Chip Select NEx low.87 88 st,fmc2-ebi-cs-address-setup-ns:89 description: This property defines the duration of the address setup90 phase in nanoseconds used for asynchronous read/write transactions.91 92 st,fmc2-ebi-cs-address-hold-ns:93 description: This property defines the duration of the address hold94 phase in nanoseconds used for asynchronous multiplexed read/write95 transactions.96 97 st,fmc2-ebi-cs-data-setup-ns:98 description: This property defines the duration of the data setup phase99 in nanoseconds used for asynchronous read/write transactions.100 101 st,fmc2-ebi-cs-bus-turnaround-ns:102 description: This property defines the delay in nanoseconds between the103 end of current read/write transaction and the next transaction.104 105 st,fmc2-ebi-cs-data-hold-ns:106 description: This property defines the duration of the data hold phase107 in nanoseconds used for asynchronous read/write transactions.108 109 st,fmc2-ebi-cs-clk-period-ns:110 description: This property defines the FMC_CLK output signal period in111 nanoseconds.112 113 st,fmc2-ebi-cs-data-latency-ns:114 description: This property defines the data latency before reading or115 writing the first data in nanoseconds.116 117 st,fmc2-ebi-cs-write-address-setup-ns:118 description: This property defines the duration of the address setup119 phase in nanoseconds used for asynchronous write transactions.120 121 st,fmc2-ebi-cs-write-address-hold-ns:122 description: This property defines the duration of the address hold123 phase in nanoseconds used for asynchronous multiplexed write124 transactions.125 126 st,fmc2-ebi-cs-write-data-setup-ns:127 description: This property defines the duration of the data setup128 phase in nanoseconds used for asynchronous write transactions.129 130 st,fmc2-ebi-cs-write-bus-turnaround-ns:131 description: This property defines the delay between the end of current132 write transaction and the next transaction in nanoseconds.133 134 st,fmc2-ebi-cs-write-data-hold-ns:135 description: This property defines the duration of the data hold phase136 in nanoseconds used for asynchronous write transactions.137 138 st,fmc2-ebi-cs-max-low-pulse-ns:139 description: This property defines the maximum chip select low pulse140 duration in nanoseconds for synchronous transactions. When this timing141 reaches 0, the controller splits the current access, toggles NE to142 allow device refresh and restarts a new access.143 144additionalProperties: true145