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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: STMicroelectronics Flexible Memory Controller 2 (FMC2)8 9description: |10 The FMC2 functional block makes the interface with: synchronous and11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped12 peripherals) and NAND flash memories.13 Its main purposes are:14 - to translate AXI transactions into the appropriate external device15 protocol16 - to meet the access time requirements of the external devices17 All external devices share the addresses, data and control signals with the18 controller. Each external device is accessed by means of a unique Chip19 Select. The FMC2 performs only one access at a time to an external device.20 21maintainers:22 - Christophe Kerello <christophe.kerello@foss.st.com>23 24properties:25 compatible:26 enum:27 - st,stm32mp1-fmc2-ebi28 - st,stm32mp25-fmc2-ebi29 30 reg:31 maxItems: 132 33 clocks:34 maxItems: 135 36 resets:37 maxItems: 138 39 power-domains:40 maxItems: 141 42 "#address-cells":43 const: 244 45 "#size-cells":46 const: 147 48 ranges:49 description: |50 Reflects the memory layout with four integer values per bank. Format:51 <bank-number> 0 <address of the bank> <size>52 53 access-controllers:54 minItems: 155 maxItems: 256 57patternProperties:58 "^.*@[0-4],[a-f0-9]+$":59 additionalProperties: true60 type: object61 $ref: mc-peripheral-props.yaml#62 63required:64 - "#address-cells"65 - "#size-cells"66 - compatible67 - reg68 - clocks69 - ranges70 71additionalProperties: false72 73examples:74 - |75 #include <dt-bindings/interrupt-controller/arm-gic.h>76 #include <dt-bindings/clock/stm32mp1-clks.h>77 #include <dt-bindings/reset/stm32mp1-resets.h>78 memory-controller@58002000 {79 #address-cells = <2>;80 #size-cells = <1>;81 compatible = "st,stm32mp1-fmc2-ebi";82 reg = <0x58002000 0x1000>;83 clocks = <&rcc FMC_K>;84 resets = <&rcc FMC_R>;85 86 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */87 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */88 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */89 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */90 <4 0 0x80000000 0x10000000>; /* NAND */91 92 psram@0,0 {93 compatible = "mtd-ram";94 reg = <0 0x00000000 0x100000>;95 bank-width = <2>;96 97 st,fmc2-ebi-cs-transaction-type = <1>;98 st,fmc2-ebi-cs-address-setup-ns = <60>;99 st,fmc2-ebi-cs-data-setup-ns = <30>;100 st,fmc2-ebi-cs-bus-turnaround-ns = <5>;101 };102 103 nand-controller@4,0 {104 #address-cells = <1>;105 #size-cells = <0>;106 compatible = "st,stm32mp1-fmc2-nfc";107 reg = <4 0x00000000 0x1000>,108 <4 0x08010000 0x1000>,109 <4 0x08020000 0x1000>,110 <4 0x01000000 0x1000>,111 <4 0x09010000 0x1000>,112 <4 0x09020000 0x1000>;113 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;114 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,115 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,116 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;117 dma-names = "tx", "rx", "ecc";118 119 nand@0 {120 reg = <0>;121 nand-on-flash-bbt;122 #address-cells = <1>;123 #size-cells = <1>;124 };125 };126 };127 128...129