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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Texas Instruments GPMC Memory Controller8 9maintainers:10 - Tony Lindgren <tony@atomide.com>11 - Roger Quadros <rogerq@kernel.org>12 13description:14 The GPMC is a unified memory controller dedicated for interfacing15 with external memory devices like16 - Asynchronous SRAM-like memories and ASICs17 - Asynchronous, synchronous, and page mode burst NOR flash18 - NAND flash19 - Pseudo-SRAM devices20 21properties:22 compatible:23 items:24 - enum:25 - ti,am3352-gpmc26 - ti,am64-gpmc27 - ti,omap2420-gpmc28 - ti,omap2430-gpmc29 - ti,omap3430-gpmc30 - ti,omap4430-gpmc31 32 reg:33 minItems: 134 maxItems: 235 36 reg-names:37 items:38 - const: cfg39 - const: data40 41 interrupts:42 maxItems: 143 44 clocks:45 maxItems: 146 description: |47 Functional clock. Used for bus timing calculations and48 GPMC configuration.49 50 clock-names:51 items:52 - const: fck53 54 power-domains:55 maxItems: 156 57 dmas:58 items:59 - description: DMA channel for GPMC NAND prefetch60 61 dma-names:62 items:63 - const: rxtx64 65 "#address-cells": true66 67 "#size-cells": true68 69 gpmc,num-cs:70 description: maximum number of supported chip-select lines.71 $ref: /schemas/types.yaml#/definitions/uint3272 73 gpmc,num-waitpins:74 description: maximum number of supported wait pins.75 $ref: /schemas/types.yaml#/definitions/uint3276 77 ranges:78 minItems: 179 description: |80 Must be set up to reflect the memory layout with four81 integer values for each chip-select line in use,82 <cs-number> 0 <physical address of mapping> <size>83 items:84 - description: NAND bank 085 - description: NOR/SRAM bank 086 - description: NOR/SRAM bank 187 88 '#interrupt-cells':89 const: 290 91 interrupt-controller:92 description: |93 The GPMC driver implements an interrupt controller for94 the NAND events "fifoevent" and "termcount" plus the95 rising/falling edges on the GPMC_WAIT pins.96 The interrupt number mapping is as follows97 0 - NAND_fifoevent98 1 - NAND_termcount99 2 - GPMC_WAIT0 pin edge100 3 - GPMC_WAIT1 pin edge, and so on.101 102 '#gpio-cells':103 const: 2104 105 gpio-controller:106 description: |107 The GPMC driver implements a GPIO controller for the108 GPMC WAIT pins that can be used as general purpose inputs.109 0 maps to GPMC_WAIT0 pin.110 111 ti,hwmods:112 description:113 Name of the HWMOD associated with GPMC. This is for legacy114 omap2/3 platforms only.115 $ref: /schemas/types.yaml#/definitions/string116 deprecated: true117 118 ti,no-idle-on-init:119 description:120 Prevent idling the module at init. This is for legacy omap2/3121 platforms only.122 type: boolean123 deprecated: true124 125patternProperties:126 "@[0-7],[a-f0-9]+$":127 type: object128 description: |129 The child device node represents the device connected to the GPMC130 bus. The device can be a NAND chip, SRAM device, NOR device131 or an ASIC.132 $ref: ti,gpmc-child.yaml133 additionalProperties: true134 135required:136 - compatible137 - reg138 - gpmc,num-cs139 - gpmc,num-waitpins140 - "#address-cells"141 - "#size-cells"142 143allOf:144 - if:145 properties:146 compatible:147 contains:148 const: ti,am64-gpmc149 then:150 required:151 - reg-names152 - power-domains153 154additionalProperties: false155 156examples:157 - |158 #include <dt-bindings/interrupt-controller/arm-gic.h>159 #include <dt-bindings/gpio/gpio.h>160 161 gpmc: memory-controller@50000000 {162 compatible = "ti,am3352-gpmc";163 reg = <0x50000000 0x2000>;164 interrupts = <100>;165 clocks = <&l3s_clkctrl>;166 clock-names = "fck";167 dmas = <&edma 52 0>;168 dma-names = "rxtx";169 gpmc,num-cs = <8>;170 gpmc,num-waitpins = <2>;171 #address-cells = <2>;172 #size-cells = <1>;173 ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */174 interrupt-controller;175 #interrupt-cells = <2>;176 gpio-controller;177 #gpio-cells = <2>;178 179 nand@0,0 {180 compatible = "ti,omap2-nand";181 reg = <0 0 4>;182 interrupt-parent = <&gpmc>;183 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */184 <1 IRQ_TYPE_NONE>; /* termcount */185 ti,nand-xfer-type = "prefetch-dma";186 ti,nand-ecc-opt = "bch16";187 ti,elm-id = <&elm>;188 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */189 };190 };191