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1* EMIF family of TI SDRAM controllers2 3EMIF - External Memory Interface - is an SDRAM controller used in4TI SoCs. EMIF supports, based on the IP revision, one or more of5DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance6of the EMIF IP and memory parts attached to it. Certain revisions7of the EMIF controller also contain optional ECC support, which8corrects one bit errors and detects two bit errors.9 10Required properties:11- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>12 is the IP revision of the specific EMIF instance. For newer controllers,13 compatible should be one of the following:14 "ti,emif-am3352"15 "ti,emif-am4372"16 "ti,emif-dra7xx"17 "ti,emif-keystone"18 19- phy-type : <u32> indicating the DDR phy type. Following are the20 allowed values21 <1> : Attila PHY22 <2> : Intelli PHY23 24- device-handle : phandle to a "lpddr2" node representing the memory part25 26- ti,hwmods : For TI hwmods processing and omap device creation27 the value shall be "emif<n>" where <n> is the number of the EMIF28 instance with base 1.29- interrupts : interrupt used by the controller30 31Required only for "ti,emif-am3352" and "ti,emif-am4372":32- sram : Phandles for generic sram driver nodes,33 first should be type 'protect-exec' for the driver to use to copy34 and run PM functions, second should be regular pool to be used for35 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml36 for more details.37 38Optional properties:39- cs1-used : Have this property if CS1 of this EMIF40 instance has a memory part attached to it. If there is a memory41 part attached to CS1, it should be the same type as the one on CS0,42 so there is no need to give the details of this memory part.43 44- cal-resistor-per-cs : Have this property if the board has one45 calibration resistor per chip-select.46 47- hw-caps-read-idle-ctrl: Have this property if the controller48 supports read idle window programming49 50- hw-caps-dll-calib-ctrl: Have this property if the controller51 supports dll calibration control52 53- hw-caps-ll-interface : Have this property if the controller54 has a low latency interface and corresponding interrupt events55 56- hw-caps-temp-alert : Have this property if the controller57 has capability for generating SDRAM temperature alerts58 59-Examples:60 61emif1: emif@4c000000 {62 compatible = "ti,emif-4d";63 ti,hwmods = "emif2";64 phy-type = <1>;65 device-handle = <&elpida_ECB240ABACN>;66 cs1-used;67 hw-caps-read-idle-ctrl;68 hw-caps-ll-interface;69 hw-caps-temp-alert;70};71 72/* From am33xx.dtsi */73emif: emif@4c000000 {74 compatible = "ti,emif-am3352";75 reg = <0x4C000000 0x1000>;76 sram = <&pm_sram_code77 &pm_sram_data>;78};79 80emif1: emif@4c000000 {81 compatible = "ti,emif-dra7xx";82 reg = <0x4c000000 0x200>;83 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;84};85