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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)8 9maintainers:10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>11 - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>12 13description:14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/15 4X memory interfaces. Versal DDR memory controller has an optional ECC support16 which correct single bit ECC errors and detect double bit ECC errors.17 18properties:19 compatible:20 const: xlnx,versal-ddrmc21 22 reg:23 items:24 - description: DDR Memory Controller registers25 - description: NOC registers corresponding to DDR Memory Controller26 27 reg-names:28 items:29 - const: base30 - const: noc31 32 interrupts:33 maxItems: 134 35required:36 - compatible37 - reg38 - reg-names39 - interrupts40 41additionalProperties: false42 43examples:44 - |45 #include <dt-bindings/interrupt-controller/arm-gic.h>46 47 bus {48 #address-cells = <2>;49 #size-cells = <2>;50 memory-controller@f6150000 {51 compatible = "xlnx,versal-ddrmc";52 reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;53 reg-names = "base", "noc";54 interrupt-parent = <&gic>;55 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;56 };57 };58