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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Allwinner A31 PRCM8 9maintainers:10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>12 13deprecated: true14 15properties:16 compatible:17 const: allwinner,sun6i-a31-prcm18 19 reg:20 maxItems: 121 22patternProperties:23 "^.*-(clk|rst)$":24 type: object25 unevaluatedProperties: false26 27 properties:28 compatible:29 enum:30 - allwinner,sun4i-a10-mod0-clk31 - allwinner,sun6i-a31-apb0-clk32 - allwinner,sun6i-a31-apb0-gates-clk33 - allwinner,sun6i-a31-ar100-clk34 - allwinner,sun6i-a31-clock-reset35 - fixed-factor-clock36 37 required:38 - compatible39 40 allOf:41 - if:42 properties:43 compatible:44 contains:45 const: fixed-factor-clock46 47 then:48 $ref: /schemas/clock/fixed-factor-clock.yaml#49 50 - if:51 properties:52 compatible:53 contains:54 const: allwinner,sun4i-a10-mod0-clk55 56 then:57 properties:58 "#clock-cells":59 const: 060 61 clocks:62 maxItems: 263 64 clock-output-names:65 maxItems: 166 67 required:68 - "#clock-cells"69 - clocks70 - clock-output-names71 72 - if:73 properties:74 compatible:75 contains:76 const: allwinner,sun6i-a31-apb0-clk77 78 then:79 properties:80 "#clock-cells":81 const: 082 83 clocks:84 maxItems: 185 86 clock-output-names:87 maxItems: 188 89 required:90 - "#clock-cells"91 - clocks92 - clock-output-names93 94 - if:95 properties:96 compatible:97 contains:98 const: allwinner,sun6i-a31-apb0-gates-clk99 100 then:101 properties:102 "#clock-cells":103 const: 1104 description: >105 This additional argument passed to that clock is the106 offset of the bit controlling this particular gate in107 the register.108 109 clocks:110 maxItems: 1111 112 clock-output-names:113 minItems: 1114 maxItems: 32115 116 required:117 - "#clock-cells"118 - clocks119 - clock-output-names120 121 - if:122 properties:123 compatible:124 contains:125 const: allwinner,sun6i-a31-ar100-clk126 127 then:128 properties:129 "#clock-cells":130 const: 0131 132 clocks:133 maxItems: 4134 description: >135 The parent order must match the hardware programming136 order.137 138 clock-output-names:139 maxItems: 1140 141 required:142 - "#clock-cells"143 - clocks144 - clock-output-names145 146 - if:147 properties:148 compatible:149 contains:150 const: allwinner,sun6i-a31-clock-reset151 152 then:153 properties:154 "#reset-cells":155 const: 1156 157 required:158 - "#reset-cells"159 160required:161 - compatible162 - reg163 164additionalProperties: false165 166examples:167 - |168 #include <dt-bindings/clock/sun6i-a31-ccu.h>169 170 prcm@1f01400 {171 compatible = "allwinner,sun6i-a31-prcm";172 reg = <0x01f01400 0x200>;173 174 ar100: ar100-clk {175 compatible = "allwinner,sun6i-a31-ar100-clk";176 #clock-cells = <0>;177 clocks = <&rtc 0>, <&osc24M>,178 <&ccu CLK_PLL_PERIPH>,179 <&ccu CLK_PLL_PERIPH>;180 clock-output-names = "ar100";181 };182 183 ahb0: ahb0-clk {184 compatible = "fixed-factor-clock";185 #clock-cells = <0>;186 clock-div = <1>;187 clock-mult = <1>;188 clocks = <&ar100>;189 clock-output-names = "ahb0";190 };191 192 apb0: apb0-clk {193 compatible = "allwinner,sun6i-a31-apb0-clk";194 #clock-cells = <0>;195 clocks = <&ahb0>;196 clock-output-names = "apb0";197 };198 199 apb0_gates: apb0-gates-clk {200 compatible = "allwinner,sun6i-a31-apb0-gates-clk";201 #clock-cells = <1>;202 clocks = <&apb0>;203 clock-output-names = "apb0_pio", "apb0_ir",204 "apb0_timer", "apb0_p2wi",205 "apb0_uart", "apb0_1wire",206 "apb0_i2c";207 };208 209 ir_clk: ir-clk {210 #clock-cells = <0>;211 compatible = "allwinner,sun4i-a10-mod0-clk";212 clocks = <&rtc 0>, <&osc24M>;213 clock-output-names = "ir";214 };215 216 apb0_rst: apb0-rst {217 compatible = "allwinner,sun6i-a31-clock-reset";218 #reset-cells = <1>;219 };220 };221 222...223