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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# # Copyright (c) 2021 Aspeed Tehchnology Inc.3%YAML 1.24---5$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: Aspeed Low Pin Count (LPC) Bus Controller9 10maintainers:11 - Andrew Jeffery <andrew@aj.id.au>12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>13 14description:15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth16 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The17 primary use case of the Aspeed LPC controller is as a slave on the bus18 (typically in a Baseboard Management Controller SoC), but under certain19 conditions it can also take the role of bus master.20 21 The LPC controller is represented as a multi-function device to account for the22 mix of functionality, which includes, but is not limited to23 24 * An IPMI Block Transfer[2] Controller25 26 * An LPC Host Interface Controller manages functions exposed to the host such27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART28 management and bus snoop configuration.29 30 * A set of SuperIO[3] scratch registers enabling implementation of e.g. custom31 hardware management protocols for handover between the host and baseboard32 management controller.33 34 Additionally the state of the LPC controller influences the pinmux35 configuration, therefore the host portion of the controller is exposed as a36 syscon as a means to arbitrate access.37 38properties:39 compatible:40 items:41 - enum:42 - aspeed,ast2400-lpc-v243 - aspeed,ast2500-lpc-v244 - aspeed,ast2600-lpc-v245 - const: simple-mfd46 - const: syscon47 48 reg:49 maxItems: 150 51 "#address-cells":52 const: 153 54 "#size-cells":55 const: 156 57 ranges: true58 59patternProperties:60 "^lpc-ctrl@[0-9a-f]+$":61 type: object62 additionalProperties: false63 64 description: |65 The LPC Host Interface Controller manages functions exposed to the host such as66 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management67 and bus snoop configuration.68 69 properties:70 compatible:71 items:72 - enum:73 - aspeed,ast2400-lpc-ctrl74 - aspeed,ast2500-lpc-ctrl75 - aspeed,ast2600-lpc-ctrl76 77 reg:78 maxItems: 179 80 clocks:81 maxItems: 182 83 memory-region:84 maxItems: 185 description: handle to memory reservation for the LPC to AHB mapping region86 87 flash:88 $ref: /schemas/types.yaml#/definitions/phandle89 description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping90 91 required:92 - compatible93 - clocks94 95 "^reset-controller@[0-9a-f]+$":96 type: object97 additionalProperties: false98 99 description:100 The UARTs present in the ASPEED SoC can have their resets tied to the reset101 state of the LPC bus. Some systems may chose to modify this configuration102 103 properties:104 compatible:105 items:106 - enum:107 - aspeed,ast2400-lpc-reset108 - aspeed,ast2500-lpc-reset109 - aspeed,ast2600-lpc-reset110 111 reg:112 maxItems: 1113 114 '#reset-cells':115 const: 1116 117 required:118 - compatible119 - '#reset-cells'120 121 "^lpc-snoop@[0-9a-f]+$":122 type: object123 additionalProperties: false124 125 description:126 The LPC snoop interface allows the BMC to listen on and record the data127 bytes written by the Host to the targeted LPC I/O pots.128 129 properties:130 compatible:131 items:132 - enum:133 - aspeed,ast2400-lpc-snoop134 - aspeed,ast2500-lpc-snoop135 - aspeed,ast2600-lpc-snoop136 137 reg:138 maxItems: 1139 140 interrupts:141 maxItems: 1142 143 snoop-ports:144 $ref: /schemas/types.yaml#/definitions/uint32-array145 description: The LPC I/O ports to snoop146 147 required:148 - compatible149 - interrupts150 - snoop-ports151 152 "^uart-routing@[0-9a-f]+$":153 $ref: /schemas/soc/aspeed/uart-routing.yaml#154 description: The UART routing control under LPC register space155 156required:157 - compatible158 - reg159 - "#address-cells"160 - "#size-cells"161 - ranges162 163additionalProperties:164 type: object165 166examples:167 - |168 #include <dt-bindings/interrupt-controller/arm-gic.h>169 #include <dt-bindings/clock/ast2600-clock.h>170 171 lpc: lpc@1e789000 {172 compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";173 reg = <0x1e789000 0x1000>;174 175 #address-cells = <1>;176 #size-cells = <1>;177 ranges = <0x0 0x1e789000 0x1000>;178 179 lpc_ctrl: lpc-ctrl@80 {180 compatible = "aspeed,ast2600-lpc-ctrl";181 reg = <0x80 0x80>;182 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;183 memory-region = <&flash_memory>;184 flash = <&spi>;185 };186 187 lpc_reset: reset-controller@98 {188 compatible = "aspeed,ast2600-lpc-reset";189 reg = <0x98 0x4>;190 #reset-cells = <1>;191 };192 193 lpc_snoop: lpc-snoop@90 {194 compatible = "aspeed,ast2600-lpc-snoop";195 reg = <0x90 0x8>;196 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;197 snoop-ports = <0x80>;198 };199 };200