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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Amlogic Meson SDHC controller8 9allOf:10 - $ref: mmc-controller.yaml11 12maintainers:13 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>14 15description: |16 The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC17 card interface with 1/4/8-bit bus width.18 It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock).19 20properties:21 compatible:22 items:23 - enum:24 - amlogic,meson8-sdhc25 - amlogic,meson8b-sdhc26 - amlogic,meson8m2-sdhc27 - const: amlogic,meson-mx-sdhc28 29 reg:30 minItems: 131 32 interrupts:33 minItems: 134 35 clocks:36 minItems: 537 38 clock-names:39 items:40 - const: clkin041 - const: clkin142 - const: clkin243 - const: clkin344 - const: pclk45 46required:47 - compatible48 - reg49 - interrupts50 - clocks51 - clock-names52 53unevaluatedProperties: false54 55examples:56 - |57 #include <dt-bindings/interrupt-controller/irq.h>58 #include <dt-bindings/interrupt-controller/arm-gic.h>59 60 sdhc: mmc@8e00 {61 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";62 reg = <0x8e00 0x42>;63 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;64 clocks = <&xtal>,65 <&fclk_div4>,66 <&fclk_div3>,67 <&fclk_div5>,68 <&sdhc_pclk>;69 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";70 };71