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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)8 9maintainers:10 - Masahiro Yamada <yamada.masahiro@socionext.com>11 12properties:13 compatible:14 items:15 - enum:16 - amd,pensando-elba-sd4hc17 - microchip,mpfs-sd4hc18 - socionext,uniphier-sd4hc19 - const: cdns,sd4hc20 21 reg:22 minItems: 123 maxItems: 224 25 interrupts:26 maxItems: 127 28 clocks:29 maxItems: 130 31 resets:32 maxItems: 133 34 # PHY DLL input delays:35 # They are used to delay the data valid window, and align the window to36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)37 # and it is increased by 2.5ns in each step.38 39 cdns,phy-input-delay-sd-highspeed:40 description: Value of the delay in the input path for SD high-speed timing41 $ref: /schemas/types.yaml#/definitions/uint3242 minimum: 043 maximum: 0x1f44 45 cdns,phy-input-delay-legacy:46 description: Value of the delay in the input path for legacy timing47 $ref: /schemas/types.yaml#/definitions/uint3248 minimum: 049 maximum: 0x1f50 51 cdns,phy-input-delay-sd-uhs-sdr12:52 description: Value of the delay in the input path for SD UHS SDR12 timing53 $ref: /schemas/types.yaml#/definitions/uint3254 minimum: 055 maximum: 0x1f56 57 cdns,phy-input-delay-sd-uhs-sdr25:58 description: Value of the delay in the input path for SD UHS SDR25 timing59 $ref: /schemas/types.yaml#/definitions/uint3260 minimum: 061 maximum: 0x1f62 63 cdns,phy-input-delay-sd-uhs-sdr50:64 description: Value of the delay in the input path for SD UHS SDR50 timing65 $ref: /schemas/types.yaml#/definitions/uint3266 minimum: 067 maximum: 0x1f68 69 cdns,phy-input-delay-sd-uhs-ddr50:70 description: Value of the delay in the input path for SD UHS DDR50 timing71 $ref: /schemas/types.yaml#/definitions/uint3272 minimum: 073 maximum: 0x1f74 75 cdns,phy-input-delay-mmc-highspeed:76 description: Value of the delay in the input path for MMC high-speed timing77 $ref: /schemas/types.yaml#/definitions/uint3278 minimum: 079 maximum: 0x1f80 81 cdns,phy-input-delay-mmc-ddr:82 description: Value of the delay in the input path for eMMC high-speed DDR timing83 84 # PHY DLL clock delays:85 # Each delay property represents the fraction of the clock period.86 # The approximate delay value will be87 # (<delay property value>/128)*sdmclk_clock_period.88 $ref: /schemas/types.yaml#/definitions/uint3289 minimum: 090 maximum: 0x1f91 92 cdns,phy-dll-delay-sdclk:93 description: |94 Value of the delay introduced on the sdclk output for all modes except95 HS200, HS400 and HS400_ES.96 $ref: /schemas/types.yaml#/definitions/uint3297 minimum: 098 maximum: 0x7f99 100 cdns,phy-dll-delay-sdclk-hsmmc:101 description: |102 Value of the delay introduced on the sdclk output for HS200, HS400 and103 HS400_ES speed modes.104 $ref: /schemas/types.yaml#/definitions/uint32105 minimum: 0106 maximum: 0x7f107 108 cdns,phy-dll-delay-strobe:109 description: |110 Value of the delay introduced on the dat_strobe input used in111 HS400 / HS400_ES speed modes.112 $ref: /schemas/types.yaml#/definitions/uint32113 minimum: 0114 maximum: 0x7f115 116required:117 - compatible118 - reg119 - interrupts120 - clocks121 122allOf:123 - $ref: mmc-controller.yaml124 - if:125 properties:126 compatible:127 contains:128 const: amd,pensando-elba-sd4hc129 then:130 properties:131 reg:132 items:133 - description: Host controller registers134 - description: Elba byte-lane enable register for writes135 required:136 - resets137 else:138 properties:139 reg:140 maxItems: 1141 142unevaluatedProperties: false143 144examples:145 - |146 emmc: mmc@5a000000 {147 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";148 reg = <0x5a000000 0x400>;149 interrupts = <0 78 4>;150 clocks = <&clk 4>;151 bus-width = <8>;152 mmc-ddr-1_8v;153 mmc-hs200-1_8v;154 mmc-hs400-1_8v;155 cdns,phy-dll-delay-sdclk = <0>;156 };157