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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX8 9maintainers:10 - Shawn Guo <shawnguo@kernel.org>11 12allOf:13 - $ref: sdhci-common.yaml#14 15description: |16 The Enhanced Secure Digital Host Controller on Freescale i.MX family17 provides an interface for MMC, SD, and SDIO types of memory cards.18 19 This file documents differences between the core properties described20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.21 22properties:23 compatible:24 oneOf:25 - enum:26 - fsl,imx25-esdhc27 - fsl,imx35-esdhc28 - fsl,imx51-esdhc29 - fsl,imx53-esdhc30 - fsl,imx6q-usdhc31 - fsl,imx6sl-usdhc32 - fsl,imx6sx-usdhc33 - fsl,imx7d-usdhc34 - fsl,imx7ulp-usdhc35 - fsl,imx8mm-usdhc36 - fsl,imxrt1050-usdhc37 - nxp,s32g2-usdhc38 - items:39 - const: fsl,imx50-esdhc40 - const: fsl,imx53-esdhc41 - items:42 - enum:43 - fsl,imx6sll-usdhc44 - fsl,imx6ull-usdhc45 - fsl,imx6ul-usdhc46 - const: fsl,imx6sx-usdhc47 - items:48 - const: fsl,imx7d-usdhc49 - const: fsl,imx6sl-usdhc50 - items:51 - enum:52 - fsl,imx8mq-usdhc53 - const: fsl,imx7d-usdhc54 - items:55 - enum:56 - fsl,imx8mn-usdhc57 - fsl,imx8mp-usdhc58 - fsl,imx8ulp-usdhc59 - fsl,imx93-usdhc60 - fsl,imx95-usdhc61 - const: fsl,imx8mm-usdhc62 - items:63 - enum:64 - fsl,imx8dxl-usdhc65 - fsl,imx8qm-usdhc66 - const: fsl,imx8qxp-usdhc67 - items:68 - enum:69 - fsl,imx8mm-usdhc70 - fsl,imx8mn-usdhc71 - fsl,imx8mp-usdhc72 - fsl,imx8qm-usdhc73 - fsl,imx8qxp-usdhc74 - const: fsl,imx7d-usdhc75 deprecated: true76 - items:77 - enum:78 - fsl,imx8mn-usdhc79 - fsl,imx8mp-usdhc80 - const: fsl,imx8mm-usdhc81 - const: fsl,imx7d-usdhc82 deprecated: true83 - items:84 - enum:85 - fsl,imx8dxl-usdhc86 - fsl,imx8qm-usdhc87 - const: fsl,imx8qxp-usdhc88 - const: fsl,imx7d-usdhc89 deprecated: true90 - items:91 - enum:92 - fsl,imxrt1170-usdhc93 - const: fsl,imxrt1050-usdhc94 - items:95 - const: nxp,s32g3-usdhc96 - const: nxp,s32g2-usdhc97 98 reg:99 maxItems: 1100 101 interrupts:102 maxItems: 1103 104 fsl,wp-controller:105 description: |106 boolean, if present, indicate to use controller internal write protection.107 type: boolean108 109 fsl,delay-line:110 $ref: /schemas/types.yaml#/definitions/uint32111 description: |112 Specify the number of delay cells for override mode.113 This is used to set the clock delay for DLL(Delay Line) on override mode114 to select a proper data sampling window in case the clock quality is not good115 because the signal path is too long on the board. Please refer to eSDHC/uSDHC116 chapter, DLL (Delay Line) section in RM for details.117 default: 0118 119 voltage-ranges:120 $ref: /schemas/types.yaml#/definitions/uint32-matrix121 description: |122 Specify the voltage range in case there are software transparent level123 shifters on the outputs of the controller. Two cells are required, first124 cell specifies minimum slot voltage (mV), second cell specifies maximum125 slot voltage (mV).126 items:127 items:128 - description: value for minimum slot voltage129 - description: value for maximum slot voltage130 maxItems: 1131 132 fsl,tuning-start-tap:133 $ref: /schemas/types.yaml#/definitions/uint32134 description: |135 Specify the start delay cell point when send first CMD19 in tuning procedure.136 default: 0137 138 fsl,tuning-step:139 $ref: /schemas/types.yaml#/definitions/uint32140 description: |141 Specify the increasing delay cell steps in tuning procedure.142 The uSDHC use one delay cell as default increasing step to do tuning process.143 This property allows user to change the tuning step to more than one delay144 cell which is useful for some special boards or cards when the default145 tuning step can't find the proper delay window within limited tuning retries.146 default: 0147 148 fsl,strobe-dll-delay-target:149 $ref: /schemas/types.yaml#/definitions/uint32150 description: |151 Specify the strobe dll control slave delay target.152 This delay target programming host controller loopback read clock, and this153 property allows user to change the delay target for the strobe input read clock.154 If not use this property, driver default set the delay target to value 7.155 Only eMMC HS400 mode need to take care of this property.156 default: 0157 158 clocks:159 maxItems: 3160 description:161 Handle clocks for the sdhc controller.162 163 clock-names:164 items:165 - const: ipg166 - const: ahb167 - const: per168 169 iommus:170 maxItems: 1171 172 power-domains:173 maxItems: 1174 175 pinctrl-names:176 oneOf:177 - minItems: 3178 items:179 - const: default180 - const: state_100mhz181 - const: state_200mhz182 - const: sleep183 - minItems: 2184 items:185 - const: default186 - const: state_100mhz187 - const: sleep188 - minItems: 1189 items:190 - const: default191 - const: sleep192 193required:194 - compatible195 - reg196 - interrupts197 198unevaluatedProperties: false199 200examples:201 - |202 mmc@70004000 {203 compatible = "fsl,imx51-esdhc";204 reg = <0x70004000 0x4000>;205 interrupts = <1>;206 fsl,wp-controller;207 };208 209 mmc@70008000 {210 compatible = "fsl,imx51-esdhc";211 reg = <0x70008000 0x4000>;212 interrupts = <2>;213 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */214 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */215 };216