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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MTK MSDC Storage Host Controller8 9maintainers:10 - Chaotian Jing <chaotian.jing@mediatek.com>11 - Wenbin Mei <wenbin.mei@mediatek.com>12 13properties:14 compatible:15 oneOf:16 - enum:17 - mediatek,mt2701-mmc18 - mediatek,mt2712-mmc19 - mediatek,mt6779-mmc20 - mediatek,mt6795-mmc21 - mediatek,mt7620-mmc22 - mediatek,mt7622-mmc23 - mediatek,mt7986-mmc24 - mediatek,mt8135-mmc25 - mediatek,mt8173-mmc26 - mediatek,mt8183-mmc27 - mediatek,mt8516-mmc28 - items:29 - const: mediatek,mt7623-mmc30 - const: mediatek,mt2701-mmc31 - items:32 - enum:33 - mediatek,mt8186-mmc34 - mediatek,mt8188-mmc35 - mediatek,mt8192-mmc36 - mediatek,mt8195-mmc37 - mediatek,mt8365-mmc38 - const: mediatek,mt8183-mmc39 40 reg:41 minItems: 142 items:43 - description: base register (required).44 - description: top base register (required for MT8183).45 46 clocks:47 description:48 Should contain phandle for the clock feeding the MMC controller.49 minItems: 250 maxItems: 751 52 clock-names:53 minItems: 254 maxItems: 755 56 interrupts:57 description:58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended59 interrupt is required and be configured as wakeup source irq.60 minItems: 161 maxItems: 262 63 interrupt-names:64 items:65 - const: msdc66 - const: sdio_wakeup67 68 pinctrl-names:69 description:70 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin71 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this72 scenario.73 minItems: 274 items:75 - const: default76 - const: state_uhs77 - const: state_eint78 79 pinctrl-0:80 description:81 should contain default/high speed pin ctrl.82 maxItems: 183 84 pinctrl-1:85 description:86 should contain uhs mode pin ctrl.87 maxItems: 188 89 pinctrl-2:90 description:91 should switch dat1 pin to GPIO mode.92 maxItems: 193 94 hs400-ds-delay:95 $ref: /schemas/types.yaml#/definitions/uint3296 description:97 HS400 DS delay setting.98 minimum: 099 maximum: 0xffffffff100 101 mediatek,hs200-cmd-int-delay:102 $ref: /schemas/types.yaml#/definitions/uint32103 description:104 HS200 command internal delay setting.105 This field has total 32 stages.106 The value is an integer from 0 to 31.107 minimum: 0108 maximum: 31109 110 mediatek,hs400-cmd-int-delay:111 $ref: /schemas/types.yaml#/definitions/uint32112 description:113 HS400 command internal delay setting.114 This field has total 32 stages.115 The value is an integer from 0 to 31.116 minimum: 0117 maximum: 31118 119 mediatek,hs400-cmd-resp-sel-rising:120 $ref: /schemas/types.yaml#/definitions/flag121 description:122 HS400 command response sample selection.123 If present, HS400 command responses are sampled on rising edges.124 If not present, HS400 command responses are sampled on falling edges.125 126 mediatek,hs400-ds-dly3:127 $ref: /schemas/types.yaml#/definitions/uint32128 description:129 Gear of the third delay line for DS for input data latch in data130 pad macro, there are 32 stages from 0 to 31.131 For different corner IC, the time is different about one step, it is132 about 100ps.133 The value is confirmed by doing scan and calibration to find a best134 value with corner IC and it is valid only for HS400 mode.135 minimum: 0136 maximum: 31137 138 mediatek,latch-ck:139 $ref: /schemas/types.yaml#/definitions/uint32140 description:141 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid142 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].143 if not present, default value is 0.144 applied to compatible "mediatek,mt2701-mmc".145 minimum: 0146 maximum: 7147 148 mediatek,tuning-step:149 $ref: /schemas/types.yaml#/definitions/uint32150 description:151 Some SoCs need extend tuning step for better delay value to avoid CRC issue.152 If not present, default tuning step is 32. For eMMC and SD, this can yield153 satisfactory calibration results in most cases.154 enum: [32, 64]155 default: 32156 157 resets:158 maxItems: 1159 160 reset-names:161 const: hrst162 163required:164 - compatible165 - reg166 - interrupts167 - clocks168 - clock-names169 - pinctrl-names170 - pinctrl-0171 - pinctrl-1172 - vmmc-supply173 - vqmmc-supply174 175allOf:176 - $ref: mmc-controller.yaml#177 - if:178 properties:179 compatible:180 enum:181 - mediatek,mt2701-mmc182 - mediatek,mt6779-mmc183 - mediatek,mt6795-mmc184 - mediatek,mt7620-mmc185 - mediatek,mt7622-mmc186 - mediatek,mt7623-mmc187 - mediatek,mt8135-mmc188 - mediatek,mt8173-mmc189 - mediatek,mt8183-mmc190 - mediatek,mt8186-mmc191 - mediatek,mt8188-mmc192 - mediatek,mt8195-mmc193 - mediatek,mt8516-mmc194 then:195 properties:196 clocks:197 minItems: 2198 items:199 - description: source clock200 - description: HCLK which used for host201 - description: independent source clock gate202 clock-names:203 minItems: 2204 items:205 - const: source206 - const: hclk207 - const: source_cg208 209 - if:210 properties:211 compatible:212 contains:213 const: mediatek,mt2712-mmc214 then:215 properties:216 clocks:217 minItems: 3218 items:219 - description: source clock220 - description: HCLK which used for host221 - description: independent source clock gate222 - description: bus clock used for internal register access (required for MSDC0/3).223 clock-names:224 minItems: 3225 items:226 - const: source227 - const: hclk228 - const: source_cg229 - const: bus_clk230 231 - if:232 properties:233 compatible:234 contains:235 const: mediatek,mt8183-mmc236 then:237 properties:238 reg:239 minItems: 2240 241 - if:242 properties:243 compatible:244 contains:245 enum:246 - mediatek,mt7986-mmc247 then:248 properties:249 clocks:250 minItems: 3251 items:252 - description: source clock253 - description: HCLK which used for host254 - description: independent source clock gate255 - description: bus clock used for internal register access (required for MSDC0/3).256 - description: msdc subsys clock gate257 clock-names:258 minItems: 3259 items:260 - const: source261 - const: hclk262 - const: source_cg263 - const: bus_clk264 - const: sys_cg265 266 - if:267 properties:268 compatible:269 enum:270 - mediatek,mt8186-mmc271 - mediatek,mt8188-mmc272 - mediatek,mt8195-mmc273 then:274 properties:275 clocks:276 items:277 - description: source clock278 - description: HCLK which used for host279 - description: independent source clock gate280 - description: crypto clock used for data encrypt/decrypt (optional)281 clock-names:282 items:283 - const: source284 - const: hclk285 - const: source_cg286 - const: crypto287 288 - if:289 properties:290 compatible:291 contains:292 const: mediatek,mt8192-mmc293 then:294 properties:295 clocks:296 items:297 - description: source clock298 - description: HCLK which used for host299 - description: independent source clock gate300 - description: msdc subsys clock gate301 - description: peripheral bus clock gate302 - description: AXI bus clock gate303 - description: AHB bus clock gate304 clock-names:305 items:306 - const: source307 - const: hclk308 - const: source_cg309 - const: sys_cg310 - const: pclk_cg311 - const: axi_cg312 - const: ahb_cg313 314unevaluatedProperties: false315 316examples:317 - |318 #include <dt-bindings/interrupt-controller/irq.h>319 #include <dt-bindings/interrupt-controller/arm-gic.h>320 #include <dt-bindings/clock/mt8173-clk.h>321 mmc0: mmc@11230000 {322 compatible = "mediatek,mt8173-mmc";323 reg = <0x11230000 0x1000>;324 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;325 vmmc-supply = <&mt6397_vemc_3v3_reg>;326 vqmmc-supply = <&mt6397_vio18_reg>;327 clocks = <&pericfg CLK_PERI_MSDC30_0>,328 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;329 clock-names = "source", "hclk";330 pinctrl-names = "default", "state_uhs";331 pinctrl-0 = <&mmc0_pins_default>;332 pinctrl-1 = <&mmc0_pins_uhs>;333 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;334 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;335 hs400-ds-delay = <0x14015>;336 mediatek,hs200-cmd-int-delay = <26>;337 mediatek,hs400-cmd-int-delay = <14>;338 mediatek,hs400-cmd-resp-sel-rising;339 };340 341 mmc3: mmc@11260000 {342 compatible = "mediatek,mt8173-mmc";343 reg = <0x11260000 0x1000>;344 clock-names = "source", "hclk";345 clocks = <&pericfg CLK_PERI_MSDC30_3>,346 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;347 interrupt-names = "msdc", "sdio_wakeup";348 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,349 <&pio 23 IRQ_TYPE_LEVEL_LOW>;350 pinctrl-names = "default", "state_uhs", "state_eint";351 pinctrl-0 = <&mmc2_pins_default>;352 pinctrl-1 = <&mmc2_pins_uhs>;353 pinctrl-2 = <&mmc2_pins_eint>;354 bus-width = <4>;355 max-frequency = <200000000>;356 cap-sd-highspeed;357 sd-uhs-sdr104;358 keep-power-in-suspend;359 wakeup-source;360 cap-sdio-irq;361 no-mmc;362 no-sd;363 non-removable;364 vmmc-supply = <&sdio_fixed_3v3>;365 vqmmc-supply = <&mt6397_vgp3_reg>;366 mmc-pwrseq = <&wifi_pwrseq>;367 };368 369...370