314 lines · yaml
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: NVIDIA Tegra Secure Digital Host Controller8 9maintainers:10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 13description: |14 This controller on Tegra family SoCs provides an interface for MMC, SD, and15 SDIO types of memory cards.16 17 This file documents differences between the core properties described by18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.19 20properties:21 compatible:22 oneOf:23 - enum:24 - nvidia,tegra20-sdhci25 - nvidia,tegra30-sdhci26 - nvidia,tegra114-sdhci27 - nvidia,tegra124-sdhci28 - nvidia,tegra210-sdhci29 - nvidia,tegra186-sdhci30 - nvidia,tegra194-sdhci31 32 - items:33 - const: nvidia,tegra132-sdhci34 - const: nvidia,tegra124-sdhci35 36 - items:37 - enum:38 - nvidia,tegra194-sdhci39 - nvidia,tegra234-sdhci40 - const: nvidia,tegra186-sdhci41 42 reg:43 maxItems: 144 45 interrupts:46 maxItems: 147 48 assigned-clocks: true49 assigned-clock-parents: true50 assigned-clock-rates: true51 52 clocks:53 minItems: 154 maxItems: 255 56 clock-names:57 minItems: 158 maxItems: 259 60 resets:61 items:62 - description: module reset63 64 reset-names:65 items:66 - const: sdhci67 68 power-gpios:69 description: specify GPIOs for power control70 maxItems: 171 72 interconnects:73 items:74 - description: memory read client75 - description: memory write client76 77 interconnect-names:78 items:79 - const: dma-mem # read80 - const: write81 82 iommus:83 maxItems: 184 85 operating-points-v2: true86 87 power-domains:88 items:89 - description: phandle to the core power domain90 91 nvidia,default-tap:92 description: Specify the default inbound sampling clock trimmer value for93 non-tunable modes.94 95 The values are used for compensating trace length differences by96 adjusting the sampling point. The values are programmed to the Vendor97 Clock Control Register. Please refer to the reference manual of the SoC98 for correct values.99 100 The DQS trim values are only used on controllers which support HS400101 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.102 $ref: /schemas/types.yaml#/definitions/uint32103 104 nvidia,default-trim:105 description: Specify the default outbound clock trimmer value.106 $ref: /schemas/types.yaml#/definitions/uint32107 108 nvidia,dqs-trim:109 description: Specify DQS trim value for HS400 timing.110 $ref: /schemas/types.yaml#/definitions/uint32111 112 nvidia,pad-autocal-pull-down-offset-1v8:113 description: Specify drive strength calibration offsets for 1.8 V114 signaling modes.115 $ref: /schemas/types.yaml#/definitions/uint32116 117 nvidia,pad-autocal-pull-down-offset-1v8-timeout:118 description: Specify drive strength used as a fallback in case the119 automatic calibration times out on a 1.8 V signaling mode.120 $ref: /schemas/types.yaml#/definitions/uint32121 122 nvidia,pad-autocal-pull-down-offset-3v3:123 description: Specify drive strength calibration offsets for 3.3 V124 signaling modes.125 $ref: /schemas/types.yaml#/definitions/uint32126 127 nvidia,pad-autocal-pull-down-offset-3v3-timeout:128 description: Specify drive strength used as a fallback in case the129 automatic calibration times out on a 3.3 V signaling mode.130 $ref: /schemas/types.yaml#/definitions/uint32131 132 nvidia,pad-autocal-pull-down-offset-sdr104:133 description: Specify drive strength calibration offsets for SDR104 mode.134 $ref: /schemas/types.yaml#/definitions/uint32135 136 nvidia,pad-autocal-pull-down-offset-hs400:137 description: Specify drive strength calibration offsets for HS400 mode.138 $ref: /schemas/types.yaml#/definitions/uint32139 140 nvidia,pad-autocal-pull-up-offset-1v8:141 description: Specify drive strength calibration offsets for 1.8 V142 signaling modes.143 $ref: /schemas/types.yaml#/definitions/uint32144 145 nvidia,pad-autocal-pull-up-offset-1v8-timeout:146 description: Specify drive strength used as a fallback in case the147 automatic calibration times out on a 1.8 V signaling mode.148 $ref: /schemas/types.yaml#/definitions/uint32149 150 nvidia,pad-autocal-pull-up-offset-3v3:151 description: Specify drive strength calibration offsets for 3.3 V152 signaling modes.153 154 The property values are drive codes which are programmed into the155 PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG156 register. A higher value corresponds to higher drive strength. Please157 refer to the reference manual of the SoC for correct values. The SDR104158 and HS400 timing specific values are used in corresponding modes if159 specified.160 $ref: /schemas/types.yaml#/definitions/uint32161 162 nvidia,pad-autocal-pull-up-offset-3v3-timeout:163 description: Specify drive strength used as a fallback in case the164 automatic calibration times out on a 3.3 V signaling mode.165 $ref: /schemas/types.yaml#/definitions/uint32166 167 nvidia,pad-autocal-pull-up-offset-sdr104:168 description: Specify drive strength calibration offsets for SDR104 mode.169 $ref: /schemas/types.yaml#/definitions/uint32170 171 nvidia,pad-autocal-pull-up-offset-hs400:172 description: Specify drive strength calibration offsets for HS400 mode.173 $ref: /schemas/types.yaml#/definitions/uint32174 175 nvidia,only-1-8v:176 description: The presence of this property indicates that the controller177 operates at a 1.8 V fixed I/O voltage.178 $ref: /schemas/types.yaml#/definitions/flag179 180required:181 - compatible182 - reg183 - interrupts184 - clocks185 - resets186 - reset-names187 188allOf:189 - $ref: mmc-controller.yaml190 - if:191 properties:192 compatible:193 contains:194 enum:195 - nvidia,tegra20-sdhci196 - nvidia,tegra30-sdhci197 - nvidia,tegra114-sdhci198 - nvidia,tegra124-sdhci199 then:200 properties:201 clocks:202 items:203 - description: module clock204 else:205 properties:206 clocks:207 items:208 - description: module clock209 - description: timeout clock210 211 clock-names:212 items:213 - const: sdhci214 - const: tmclk215 required:216 - clock-names217 218 - if:219 properties:220 compatible:221 contains:222 const: nvidia,tegra210-sdhci223 then:224 properties:225 pinctrl-names:226 oneOf:227 - items:228 - const: sdmmc-3v3229 description: pad configuration for 3.3 V230 - const: sdmmc-1v8231 description: pad configuration for 1.8 V232 - const: sdmmc-3v3-drv233 description: pull-up/down configuration for 3.3 V234 - const: sdmmc-1v8-drv235 description: pull-up/down configuration for 1.8 V236 - items:237 - const: sdmmc-3v3-drv238 description: pull-up/down configuration for 3.3 V239 - const: sdmmc-1v8-drv240 description: pull-up/down configuration for 1.8 V241 - items:242 - const: sdmmc-1v8-drv243 description: pull-up/down configuration for 1.8 V244 required:245 - clock-names246 - if:247 properties:248 compatible:249 contains:250 enum:251 - nvidia,tegra186-sdhci252 - nvidia,tegra194-sdhci253 then:254 properties:255 pinctrl-names:256 items:257 - const: sdmmc-3v3258 description: pad configuration for 3.3 V259 - const: sdmmc-1v8260 description: pad configuration for 1.8 V261 required:262 - clock-names263 264unevaluatedProperties: false265 266examples:267 - |268 #include <dt-bindings/interrupt-controller/arm-gic.h>269 270 mmc@c8000200 {271 compatible = "nvidia,tegra20-sdhci";272 reg = <0xc8000200 0x200>;273 interrupts = <47>;274 clocks = <&tegra_car 14>;275 resets = <&tegra_car 14>;276 reset-names = "sdhci";277 cd-gpios = <&gpio 69 0>; /* gpio PI5 */278 wp-gpios = <&gpio 57 0>; /* gpio PH1 */279 power-gpios = <&gpio 155 0>; /* gpio PT3 */280 bus-width = <8>;281 };282 283 - |284 #include <dt-bindings/clock/tegra210-car.h>285 #include <dt-bindings/interrupt-controller/arm-gic.h>286 287 mmc@700b0000 {288 compatible = "nvidia,tegra210-sdhci";289 reg = <0x700b0000 0x200>;290 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;291 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,292 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;293 clock-names = "sdhci", "tmclk";294 resets = <&tegra_car 14>;295 reset-names = "sdhci";296 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",297 "sdmmc-3v3-drv", "sdmmc-1v8-drv";298 pinctrl-0 = <&sdmmc1_3v3>;299 pinctrl-1 = <&sdmmc1_1v8>;300 pinctrl-2 = <&sdmmc1_3v3_drv>;301 pinctrl-3 = <&sdmmc1_1v8_drv>;302 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;303 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;304 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;305 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;306 nvidia,default-tap = <0x2>;307 nvidia,default-trim = <0x4>;308 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,309 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,310 <&tegra_car TEGRA210_CLK_PLL_C4>;311 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;312 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;313 };314