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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title:8 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile9 Storage Host Controller10 11maintainers:12 - Jaehoon Chung <jh80.chung@samsung.com>13 - Krzysztof Kozlowski <krzk@kernel.org>14 15properties:16 compatible:17 oneOf:18 - enum:19 - axis,artpec8-dw-mshc20 - samsung,exynos4210-dw-mshc21 - samsung,exynos4412-dw-mshc22 - samsung,exynos5250-dw-mshc23 - samsung,exynos5420-dw-mshc24 - samsung,exynos5420-dw-mshc-smu25 - samsung,exynos7-dw-mshc26 - samsung,exynos7-dw-mshc-smu27 - items:28 - enum:29 - samsung,exynos5433-dw-mshc-smu30 - samsung,exynos7885-dw-mshc-smu31 - samsung,exynos850-dw-mshc-smu32 - const: samsung,exynos7-dw-mshc-smu33 34 reg:35 maxItems: 136 37 interrupts:38 maxItems: 139 40 clocks:41 maxItems: 242 description:43 Handle to "biu" and "ciu" clocks for the44 bus interface unit clock and the card interface unit clock.45 46 clock-names:47 items:48 - const: biu49 - const: ciu50 51 samsung,dw-mshc-ciu-div:52 $ref: /schemas/types.yaml#/definitions/uint3253 minimum: 054 maximum: 755 description:56 The divider value for the card interface unit (ciu) clock.57 58 samsung,dw-mshc-ddr-timing:59 $ref: /schemas/types.yaml#/definitions/uint32-array60 items:61 - description: CIU clock phase shift value for tx mode62 minimum: 063 maximum: 764 - description: CIU clock phase shift value for rx mode65 minimum: 066 maximum: 767 description:68 The value of CUI clock phase shift value in transmit mode and CIU clock69 phase shift value in receive mode for double data rate mode operation.70 See also samsung,dw-mshc-hs400-timing property.71 72 samsung,dw-mshc-hs400-timing:73 $ref: /schemas/types.yaml#/definitions/uint32-array74 items:75 - description: CIU clock phase shift value for tx mode76 minimum: 077 maximum: 778 - description: CIU clock phase shift value for rx mode79 minimum: 080 maximum: 781 description: |82 The value of CIU TX and RX clock phase shift value for HS400 mode83 operation.84 Valid values for SDR and DDR CIU clock timing::85 - valid value for tx phase shift and rx phase shift is 0 to 7.86 - when CIU clock divider value is set to 3, all possible 8 phase shift87 values can be used.88 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx89 phase shift clocks should be 0.90 If missing, values from samsung,dw-mshc-ddr-timing property are used.91 92 samsung,dw-mshc-sdr-timing:93 $ref: /schemas/types.yaml#/definitions/uint32-array94 items:95 - description: CIU clock phase shift value for tx mode96 minimum: 097 maximum: 798 - description: CIU clock phase shift value for rx mode99 minimum: 0100 maximum: 7101 description:102 The value of CIU clock phase shift value in transmit mode and CIU clock103 phase shift value in receive mode for single data rate mode operation.104 See also samsung,dw-mshc-hs400-timing property.105 106 samsung,read-strobe-delay:107 $ref: /schemas/types.yaml#/definitions/uint32108 description:109 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay110 line in Read path). If missing, default from hardware is used.111 112required:113 - compatible114 - reg115 - interrupts116 - clocks117 - clock-names118 - samsung,dw-mshc-ddr-timing119 - samsung,dw-mshc-sdr-timing120 121allOf:122 - $ref: synopsys-dw-mshc-common.yaml#123 - if:124 properties:125 compatible:126 contains:127 enum:128 - samsung,exynos5250-dw-mshc129 - samsung,exynos5420-dw-mshc130 - samsung,exynos7-dw-mshc131 - samsung,exynos7-dw-mshc-smu132 - axis,artpec8-dw-mshc133 then:134 required:135 - samsung,dw-mshc-ciu-div136 137unevaluatedProperties: false138 139examples:140 - |141 #include <dt-bindings/clock/exynos5420.h>142 #include <dt-bindings/interrupt-controller/arm-gic.h>143 144 mmc@12220000 {145 compatible = "samsung,exynos5420-dw-mshc";146 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;147 #address-cells = <1>;148 #size-cells = <0>;149 reg = <0x12220000 0x1000>;150 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;151 clock-names = "biu", "ciu";152 fifo-depth = <0x40>;153 card-detect-delay = <200>;154 samsung,dw-mshc-ciu-div = <3>;155 samsung,dw-mshc-sdr-timing = <0 4>;156 samsung,dw-mshc-ddr-timing = <0 2>;157 pinctrl-names = "default";158 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;159 bus-width = <4>;160 cap-sd-highspeed;161 max-frequency = <200000000>;162 vmmc-supply = <&ldo19_reg>;163 vqmmc-supply = <&ldo13_reg>;164 sd-uhs-sdr50;165 sd-uhs-sdr104;166 sd-uhs-ddr50;167 };168