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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/3%YAML 1.24---5$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#6$schema: http://devicetree.org/meta-schemas/core.yaml#7 8title: TI AM654 MMC Controller9 10maintainers:11 - Ulf Hansson <ulf.hansson@linaro.org>12 13allOf:14 - $ref: sdhci-common.yaml#15 16properties:17 compatible:18 oneOf:19 - enum:20 - ti,am62-sdhci21 - ti,am64-sdhci-4bit22 - ti,am64-sdhci-8bit23 - ti,am654-sdhci-5.124 - ti,j721e-sdhci-4bit25 - ti,j721e-sdhci-8bit26 - items:27 - const: ti,j7200-sdhci-8bit28 - const: ti,j721e-sdhci-8bit29 - items:30 - const: ti,j7200-sdhci-4bit31 - const: ti,j721e-sdhci-4bit32 33 reg:34 maxItems: 235 36 interrupts:37 maxItems: 138 39 power-domains:40 maxItems: 141 42 clocks:43 minItems: 144 maxItems: 245 description: Handles to input clocks46 47 clock-names:48 minItems: 149 items:50 - const: clk_ahb51 - const: clk_xin52 53 dma-coherent:54 type: boolean55 56 # PHY output tap delays:57 # Used to delay the data valid window and align it to the sampling clock.58 # Binding needs to be provided for each supported speed mode otherwise the59 # corresponding mode will be disabled.60 61 ti,otap-del-sel-legacy:62 description: Output tap delay for SD/MMC legacy timing63 $ref: /schemas/types.yaml#/definitions/uint3264 minimum: 065 maximum: 0xf66 67 ti,otap-del-sel-mmc-hs:68 description: Output tap delay for MMC high speed timing69 $ref: /schemas/types.yaml#/definitions/uint3270 minimum: 071 maximum: 0xf72 73 ti,otap-del-sel-sd-hs:74 description: Output tap delay for SD high speed timing75 $ref: /schemas/types.yaml#/definitions/uint3276 minimum: 077 maximum: 0xf78 79 ti,otap-del-sel-sdr12:80 description: Output tap delay for SD UHS SDR12 timing81 $ref: /schemas/types.yaml#/definitions/uint3282 minimum: 083 maximum: 0xf84 85 ti,otap-del-sel-sdr25:86 description: Output tap delay for SD UHS SDR25 timing87 $ref: /schemas/types.yaml#/definitions/uint3288 minimum: 089 maximum: 0xf90 91 ti,otap-del-sel-sdr50:92 description: Output tap delay for SD UHS SDR50 timing93 $ref: /schemas/types.yaml#/definitions/uint3294 minimum: 095 maximum: 0xf96 97 ti,otap-del-sel-sdr104:98 description: Output tap delay for SD UHS SDR104 timing99 $ref: /schemas/types.yaml#/definitions/uint32100 minimum: 0101 maximum: 0xf102 103 ti,otap-del-sel-ddr50:104 description: Output tap delay for SD UHS DDR50 timing105 $ref: /schemas/types.yaml#/definitions/uint32106 minimum: 0107 maximum: 0xf108 109 ti,otap-del-sel-ddr52:110 description: Output tap delay for eMMC DDR52 timing111 $ref: /schemas/types.yaml#/definitions/uint32112 minimum: 0113 maximum: 0xf114 115 ti,otap-del-sel-hs200:116 description: Output tap delay for eMMC HS200 timing117 $ref: /schemas/types.yaml#/definitions/uint32118 minimum: 0119 maximum: 0xf120 121 ti,otap-del-sel-hs400:122 description: Output tap delay for eMMC HS400 timing123 $ref: /schemas/types.yaml#/definitions/uint32124 minimum: 0125 maximum: 0xf126 127 # PHY input tap delays:128 # Used to delay the data valid window and align it to the sampling clock for129 # modes that don't support tuning130 131 ti,itap-del-sel-legacy:132 description: Input tap delay for SD/MMC legacy timing133 $ref: /schemas/types.yaml#/definitions/uint32134 minimum: 0135 maximum: 0x1f136 137 ti,itap-del-sel-mmc-hs:138 description: Input tap delay for MMC high speed timing139 $ref: /schemas/types.yaml#/definitions/uint32140 minimum: 0141 maximum: 0x1f142 143 ti,itap-del-sel-sd-hs:144 description: Input tap delay for SD high speed timing145 $ref: /schemas/types.yaml#/definitions/uint32146 minimum: 0147 maximum: 0x1f148 149 ti,itap-del-sel-sdr12:150 description: Input tap delay for SD UHS SDR12 timing151 $ref: /schemas/types.yaml#/definitions/uint32152 minimum: 0153 maximum: 0x1f154 155 ti,itap-del-sel-sdr25:156 description: Input tap delay for SD UHS SDR25 timing157 $ref: /schemas/types.yaml#/definitions/uint32158 minimum: 0159 maximum: 0x1f160 161 ti,itap-del-sel-ddr50:162 description: Input tap delay for MMC DDR50 timing163 $ref: /schemas/types.yaml#/definitions/uint32164 minimum: 0165 maximum: 0x1f166 167 ti,itap-del-sel-ddr52:168 description: Input tap delay for MMC DDR52 timing169 $ref: /schemas/types.yaml#/definitions/uint32170 minimum: 0171 maximum: 0x1f172 173 ti,trm-icp:174 description: DLL trim select175 $ref: /schemas/types.yaml#/definitions/uint32176 minimum: 0177 maximum: 0xf178 179 ti,driver-strength-ohm:180 description: DLL drive strength in ohms181 $ref: /schemas/types.yaml#/definitions/uint32182 enum:183 - 33184 - 40185 - 50186 - 66187 - 100188 189 ti,strobe-sel:190 description: strobe select delay for HS400 speed mode.191 $ref: /schemas/types.yaml#/definitions/uint32192 193 ti,clkbuf-sel:194 description: Clock Delay Buffer Select195 $ref: /schemas/types.yaml#/definitions/uint32196 197 ti,fails-without-test-cd:198 $ref: /schemas/types.yaml#/definitions/flag199 description:200 When present, indicates that the CD line is not connected201 and the controller is required to be forced into Test mode202 to set the TESTCD bit.203 204required:205 - compatible206 - reg207 - interrupts208 - clocks209 - clock-names210 - ti,otap-del-sel-legacy211 212unevaluatedProperties: false213 214examples:215 - |216 #include <dt-bindings/interrupt-controller/irq.h>217 #include <dt-bindings/interrupt-controller/arm-gic.h>218 219 bus {220 #address-cells = <2>;221 #size-cells = <2>;222 223 mmc0: mmc@4f80000 {224 compatible = "ti,am654-sdhci-5.1";225 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;226 power-domains = <&k3_pds 47>;227 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;228 clock-names = "clk_ahb", "clk_xin";229 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;230 sdhci-caps-mask = <0x80000007 0x0>;231 mmc-ddr-1_8v;232 ti,otap-del-sel-legacy = <0x0>;233 ti,otap-del-sel-mmc-hs = <0x0>;234 ti,otap-del-sel-ddr52 = <0x5>;235 ti,otap-del-sel-hs200 = <0x5>;236 ti,otap-del-sel-hs400 = <0x0>;237 ti,itap-del-sel-legacy = <0x10>;238 ti,itap-del-sel-mmc-hs = <0xa>;239 ti,itap-del-sel-ddr52 = <0x3>;240 ti,trm-icp = <0x8>;241 };242 };243