113 lines · yaml
1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause2%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Spreadtrum SDHCI controller8 9maintainers:10 - Orson Zhai <orsonzhai@gmail.com>11 - Baolin Wang <baolin.wang7@gmail.com>12 - Chunyan Zhang <zhang.lyra@gmail.com>13 14properties:15 compatible:16 const: sprd,sdhci-r1117 18 reg:19 maxItems: 120 21 interrupts:22 maxItems: 123 24 clocks:25 minItems: 226 items:27 - description: SDIO source clock28 - description: gate clock for enabling/disabling the device29 - description: gate clock controlling the device for some special platforms (optional)30 31 clock-names:32 minItems: 233 items:34 - const: sdio35 - const: enable36 - const: 2x_enable37 38 pinctrl-0:39 description: default/high speed pin control40 maxItems: 141 42 pinctrl-1:43 description: UHS mode pin control44 maxItems: 145 46 pinctrl-names:47 minItems: 148 items:49 - const: default50 - const: state_uhs51 52patternProperties:53 "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$":54 $ref: /schemas/types.yaml#/definitions/uint32-array55 items:56 - description: clock data write line delay value57 - description: clock read command line delay value58 - description: clock read data positive edge delay value59 - description: clock read data negative edge delay value60 description:61 PHY DLL delays are used to delay the data valid window, and align62 the window to the sampling clock. Each cell's delay value unit is63 cycle of the PHY clock.64 65required:66 - compatible67 - reg68 - interrupts69 - clocks70 - clock-names71 72allOf:73 - $ref: sdhci-common.yaml#74 75unevaluatedProperties: false76 77examples:78 - |79 #include <dt-bindings/clock/sprd,sc9860-clk.h>80 #include <dt-bindings/interrupt-controller/arm-gic.h>81 #include <dt-bindings/interrupt-controller/irq.h>82 83 mmc@50430000 {84 compatible = "sprd,sdhci-r11";85 reg = <0x50430000 0x1000>;86 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;87 88 clocks = <&aon_prediv CLK_EMMC_2X>,89 <&apahb_gate CLK_EMMC_EB>,90 <&aon_gate CLK_EMMC_2X_EN>;91 clock-names = "sdio", "enable", "2x_enable";92 93 pinctrl-0 = <&sd0_pins_default>;94 pinctrl-1 = <&sd0_pins_uhs>;95 pinctrl-names = "default", "state_uhs";96 97 bus-width = <8>;98 cap-mmc-hw-reset;99 mmc-hs400-enhanced-strobe;100 mmc-hs400-1_8v;101 mmc-hs200-1_8v;102 mmc-ddr-1_8v;103 non-removable;104 no-sdio;105 no-sd;106 107 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>;108 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>;109 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>;110 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>;111 };112...113