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1# SPDX-License-Identifier: GPL-2.02%YAML 1.23---4$id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: Synopsys Designware Mobile Storage Host Controller8 9maintainers:10 - Ulf Hansson <ulf.hansson@linaro.org>11 12# Everything else is described in the common file13properties:14 compatible:15 enum:16 - altr,socfpga-dw-mshc17 - img,pistachio-dw-mshc18 - snps,dw-mshc19 20 reg:21 maxItems: 122 23 interrupts:24 maxItems: 125 26 clocks:27 minItems: 228 maxItems: 229 description:30 Handle to "biu" and "ciu" clocks for the31 bus interface unit clock and the card interface unit clock.32 33 clock-names:34 items:35 - const: biu36 - const: ciu37 38 iommus:39 maxItems: 140 41 altr,sysmgr-syscon:42 $ref: /schemas/types.yaml#/definitions/phandle-array43 items:44 - items:45 - description: phandle to the sysmgr node46 - description: register offset that controls the SDMMC clock phase47 - description: register shift for the smplsel(drive in) setting48 description:49 This property is optional. Contains the phandle to System Manager block50 that contains the SDMMC clock-phase control register. The first value is51 the pointer to the sysmgr, the 2nd value is the register offset for the52 SDMMC clock phase register, and the 3rd value is the bit shift for the53 smplsel(drive in) setting.54 55allOf:56 - $ref: synopsys-dw-mshc-common.yaml#57 58 - if:59 properties:60 compatible:61 contains:62 const: altr,socfpga-dw-mshc63 then:64 properties:65 altr,sysmgr-syscon: true66 else:67 properties:68 iommus: false69 altr,sysmgr-syscon: false70 71required:72 - compatible73 - reg74 - interrupts75 - clocks76 - clock-names77 78unevaluatedProperties: false79 80examples:81 - |82 mmc@12200000 {83 compatible = "snps,dw-mshc";84 reg = <0x12200000 0x1000>;85 interrupts = <0 75 0>;86 clocks = <&clock 351>, <&clock 132>;87 clock-names = "biu", "ciu";88 dmas = <&pdma 12>;89 dma-names = "rx-tx";90 resets = <&rst 20>;91 reset-names = "reset";92 vmmc-supply = <&buck8>;93 #address-cells = <1>;94 #size-cells = <0>;95 broken-cd;96 bus-width = <8>;97 cap-mmc-highspeed;98 cap-sd-highspeed;99 card-detect-delay = <200>;100 max-frequency = <200000000>;101 clock-frequency = <400000000>;102 data-addr = <0x200>;103 fifo-depth = <0x80>;104 fifo-watermark-aligned;105 };106