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1* Cadence NAND controller2 3Required properties:4 - compatible : "cdns,hp-nfc"5 - reg : Contains two entries, each of which is a tuple consisting of a6 physical address and length. The first entry is the address and7 length of the controller register set. The second entry is the8 address and length of the Slave DMA data port.9 - reg-names: should contain "reg" and "sdma"10 - #address-cells: should be 1. The cell encodes the chip select connection.11 - #size-cells : should be 0.12 - interrupts : The interrupt number.13 - clocks: phandle of the controller core clock (nf_clk).14 15Optional properties:16 - dmas: shall reference DMA channel associated to the NAND controller17 - cdns,board-delay-ps : Estimated Board delay. The value includes the total18 round trip delay for the signals and is used for deciding on values19 associated with data read capture. The example formula for SDR mode is20 the following:21 board delay = RE#PAD delay + PCB trace to device + PCB trace from device22 + DQ PAD delay23 24Child nodes represent the available NAND chips.25 26Required properties of NAND chips:27 - reg: shall contain the native Chip Select ids from 0 to max supported by28 the cadence nand flash controller29 30See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on31generic bindings.32 33Example:34 35nand_controller: nand-controller@60000000 {36 compatible = "cdns,hp-nfc";37 #address-cells = <1>;38 #size-cells = <0>;39 reg = <0x60000000 0x10000>, <0x80000000 0x10000>;40 reg-names = "reg", "sdma";41 clocks = <&nf_clk>;42 cdns,board-delay-ps = <4830>;43 interrupts = <2 0>;44 nand@0 {45 reg = <0>;46 label = "nand-1";47 };48 nand@1 {49 reg = <1>;50 label = "nand-2";51 };52 53};54