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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2%YAML 1.23---4$id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#5$schema: http://devicetree.org/meta-schemas/core.yaml#6 7title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)8 9maintainers:10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>11 12properties:13 compatible:14 enum:15 - mediatek,mt2701-nfc16 - mediatek,mt2712-nfc17 - mediatek,mt7622-nfc18 19 reg:20 items:21 - description: Base physical address and size of NFI.22 23 interrupts:24 items:25 - description: NFI interrupt26 27 clocks:28 items:29 - description: clock used for the controller30 - description: clock used for the pad31 32 clock-names:33 items:34 - const: nfi_clk35 - const: pad_clk36 37 ecc-engine:38 description: device-tree node of the required ECC engine.39 $ref: /schemas/types.yaml#/definitions/phandle40 41patternProperties:42 "^nand@[a-f0-9]$":43 $ref: raw-nand-chip.yaml#44 unevaluatedProperties: false45 properties:46 reg:47 maximum: 148 nand-ecc-mode:49 const: hw50 51allOf:52 - $ref: nand-controller.yaml#53 54 - if:55 properties:56 compatible:57 contains:58 const: mediatek,mt2701-nfc59 then:60 patternProperties:61 "^nand@[a-f0-9]$":62 properties:63 nand-ecc-step-size:64 enum: [ 512, 1024 ]65 nand-ecc-strength:66 enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,67 40, 44, 48, 52, 56, 60]68 69 - if:70 properties:71 compatible:72 contains:73 const: mediatek,mt2712-nfc74 then:75 patternProperties:76 "^nand@[a-f0-9]$":77 properties:78 nand-ecc-step-size:79 enum: [ 512, 1024 ]80 nand-ecc-strength:81 enum: [4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36,82 40, 44, 48, 52, 56, 60, 68, 72, 80]83 84 - if:85 properties:86 compatible:87 contains:88 const: mediatek,mt7622-nfc89 then:90 patternProperties:91 "^nand@[a-f0-9]$":92 properties:93 nand-ecc-step-size:94 const: 51295 nand-ecc-strength:96 enum: [4, 6, 8, 10, 12]97 98required:99 - compatible100 - reg101 - interrupts102 - clocks103 - clock-names104 - ecc-engine105 106unevaluatedProperties: false107 108examples:109 - |110 #include <dt-bindings/clock/mt2701-clk.h>111 #include <dt-bindings/interrupt-controller/arm-gic.h>112 #include <dt-bindings/interrupt-controller/irq.h>113 114 soc {115 #address-cells = <2>;116 #size-cells = <2>;117 118 nand-controller@1100d000 {119 compatible = "mediatek,mt2701-nfc";120 reg = <0 0x1100d000 0 0x1000>;121 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;122 clocks = <&pericfg CLK_PERI_NFI>,123 <&pericfg CLK_PERI_NFI_PAD>;124 clock-names = "nfi_clk", "pad_clk";125 ecc-engine = <&bch>;126 #address-cells = <1>;127 #size-cells = <0>;128 129 nand@0 {130 reg = <0>;131 132 nand-on-flash-bbt;133 nand-ecc-mode = "hw";134 nand-ecc-step-size = <1024>;135 nand-ecc-strength = <24>;136 137 partitions {138 compatible = "fixed-partitions";139 #address-cells = <1>;140 #size-cells = <1>;141 142 preloader@0 {143 label = "pl";144 read-only;145 reg = <0x0 0x400000>;146 };147 android@400000 {148 label = "android";149 reg = <0x400000 0x12c00000>;150 };151 };152 };153 };154 };155